TCI6636K2H Datasheet, PDF (278/362 Pages) Texas Instruments – Multicore DSP+ARM KeyStone II System-on-Chip (SoC)

TCI6636K2H
Multicore DSP+ARM KeyStone II System-on-Chip (SoC)
SPRS835F—October 2013
A system power monitoring solution is needed to shut down power to the board if a power supply fails. Long-term
exposure to an environment in which one of the power supply voltages is no longer present will affect the reliability
of the device. Holding the device in reset is not an acceptable solution because prolonged periods of time with an
active reset can affect long term reliability.
10.2.3 Power Supply Decoupling and Bulk Capacitors
To properly decouple the supply planes on the PCB from system noise, decoupling and bulk capacitors are required.
Bulk capacitors are used to minimize the effects of low-frequency current transients and decoupling or bypass
capacitors are used to minimize higher frequency noise. For recommendations on selection of power supply
decoupling and bulk capacitors see the Hardware Design Guide for KeyStone II Devices (in development).
10.2.4 SmartReflex
Increasing the device complexity increases its power consumption. With higher clock rates and increased
performance comes an inevitable penalty: increasing leakage currents. Leakage currents are present in any powered
circuit, independent of clock rates and usage scenarios. This static power consumption is mainly determined by
transistor type and process technology. Higher clock rates also increase dynamic power, which is the power used
when transistors switch. The dynamic power depends mainly on a specific usage scenario, clock rates, and I/O
activity.
Texas Instruments SmartReflex technology is used to decrease both static and dynamic power consumption while
maintaining the device performance. SmartReflex in the TCI6636K2H device is a feature that allows the core voltage
to be optimized based on the process corner of the device. This requires a voltage regulator for each TCI6636K2H
device.
To help maximize performance and minimize power consumption of the device, SmartReflex is required to be
implemented. The voltage selection can be accomplished using 4 VCNTL pins or 6 VCNTL pins (depending on
power supply device being used), which are used to select the output voltage of the core voltage regulator.
For information on implementation of SmartReflex see the DSP Power Consumption Summary for KeyStone Devices
Application Report and the Hardware Design Guide for KeyStone II Devices (in development).
Table 10-5 SmartReflex 4-Pin 6-bit VID Interface Switching Characteristics
(see Figure 10-3)
No.
Parameter
1 td(VCNTL[2:0]-VCNTL[3]) Delay time - VCNTL[2:0] valid after VCNTL[3] low
2 toh(VCNTL[3]-VCNTL[2:0]) Output hold time - VCNTL[2:0] valid after VCNTL[3]
3 td(VCNTL[2:0]-VCNTL[3]) Delay time - VCNTL[2:0] valid after VCNTL[3] high
4 toh(VCNTL[3]-VCNTL[2:0) Output hold time - VCNTL[2:0] valid after VCNTL[3] high
End of Table 10-5
1 C = 1/SYSCLK1 frequency (See Figure 10-9)in ms
Min
Max
Unit
300.00 ns
0.07 172020C ⁽¹⁾ ms
300.00 ns
0.07 172020C ms
278 TCI6636K2H Peripheral Information and Electrical Specifications
Copyright 2013 Texas Instruments Incorporated
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