TCI6636K2H Datasheet, PDF (248/362 Pages) Texas Instruments – Multicore DSP+ARM KeyStone II System-on-Chip (SoC)

TCI6636K2H
Multicore DSP+ARM KeyStone II System-on-Chip (SoC)
SPRS835F—October 2013
The host interrupt output pulse is stretched so that it is asserted for four bootcfg clock cycles (SYSCLK1/6) followed
by a deassertion of four bootcfg clock cycles. Generating the pulse results in a pulse-blocking window that is eight
SYSCLK1/6-cycles long. Back-to-back writes to the IPCRGH register with the IPCG bit (bit 0) set, generates only
one pulse if the back-to-back writes to IPCGRH are less than the eight SYSCLK1/6 cycle window — the pulse
blocking window. To generate back-to-back pulses, the back-to-back writes to the IPCGRH register must be written
after the eight SYSCLK1/6 cycle pulse-blocking window has elapsed. The IPC Generation Host Register is shown in
Figure 8-25 and described in Table 8-43.
Figure 8-25 IPC Generation Registers (IPCGRH)
31
30
29
28 27
87
6
5
43
10
SRCS27 SRCS26 SRCS25 SRCS24
SRCS23 – SRCS4
SRCS3 SRCS2 SRCS1 SRCS0
Reserved
IPCG
RW +0 RW +0 RW +0 RW +0
RW +0 (per bit field)
RW +0 RW +0 RW +0 RW +0
R-000
RW +0
Legend: R = Read only; RW = Read/Write; -n = value after reset
Table 8-43 IPC Generation Registers Field Descriptions
Bit Field
31-4 SRCSx
3-1 Reserved
0
IPCG
End of Table 8-43
Description
Reads return current value of internal register bit.
Writes:
0 = No effect
1 = Sets both SRCSx and the corresponding SRCCx.
Reserved
Reads return 0.
Writes:
0 = No effect
1 = Creates an interrupt pulse on device pin (host interrupt/event output in HOUT pin)
8.2.3.15 IPC Acknowledgement Host (IPCARH) Register
The IPCARH register facilitates external host interrupts. Operation and use of the IPCARH register is the same as
for other IPCAR registers. The IPC Acknowledgement Host Register is shown in Figure 8-26 and described in
Table 8-44.
Figure 8-26 IPC Acknowledgement Register (IPCARH)
31
30
29
28 27
87
6
5
43
0
SRCC27 SRCC26 SRCC25 SRCC24
SRCC23 – SRCC4
SRCC3 SRCC2 SRCC1 SRCC0
Reserved
RW +0 RW +0 RW +0 RW +0
RW +0 (per bit field)
RW +0 RW +0 RW +0 RW +0
R-0000
Legend: R = Read only; RW = Read/Write; -n = value after reset
Table 8-44 IPC Acknowledgement Register Field Descriptions
Bit Field
31-4 SRCCx
3-0 Reserved
End of Table 8-44
Description
Reads the return current value of the internal register bit.
Writes:
0 = No effect
1 = Clears both SRCCx and the corresponding SRCSx
Reserved
248 Device Boot and Configuration
Copyright 2013 Texas Instruments Incorporated
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