TCI6636K2H Datasheet, PDF (220/362 Pages) Texas Instruments – Multicore DSP+ARM KeyStone II System-on-Chip (SoC)

TCI6636K2H
Multicore DSP+ARM KeyStone II System-on-Chip (SoC)
SPRS835F—October 2013
8.1.2.3.1 PCIe Boot Device Configuration
Figure 8-10 PCIe Boot Device Configuration Fields
DEVSTAT Boot Mode Pins ROM Mapping
16
15 14 13 12 11 10 9
8
765
Ref clk
Bar Config
Reserved
Boot Master=1
Sys PLL Cfg
Ref clk
Bar Config
ARM PLL Cfg
Boot Master=0
Sys PLL Cfg
4321
0110
0110
0
Lendian
Lendian
Table 8-12 PCIe Boot Device Configuration Field Descriptions
Bit
Field
Description
16
Ref clk
PCIe Reference clock frequency
0 = 100MHz
1 = Reserved
15-12 Bar Config
PCIe BAR registers configuration
This value can range from 0 to 0xf. See Table 8-13.
11-9 Reserved/ARM PLL
Setting
When Boot Master =0 (ARM is Boot Master), pin[11:9] used as ARM PLL Setting. The PLL default settings are
determined by the [11:9] bits. This will set the PLL to the maximum clock setting for the device. Table 8-27 shows
settings for various input clock frequencies.
When Boot Master =1 (C66x is Boot Master), pin [10:9] are reserved.
8
Boot Master
Boot Master select
0 = ARM is boot master (default)
1 = C66x is boot master
7-5
SYS PLL Setting
The PLL default settings are determined by the [7:5] bits.This will set the PLL to the maximum clock setting for the
device. Default system reference clock is 156.25 MHz. Table 8-27 shows settings for various input clock
frequencies.
4-1
Boot Devices
Boot Devices[4:1]
0110 = PCIe boot mode
Others = Other boot modes
0
Lendian
End of Table 8-12
Endianess
0 = Big endian
1 = Little endian
220 Device Boot and Configuration
Copyright 2013 Texas Instruments Incorporated
Submit Documentation Feedback