TCI6636K2H Datasheet, PDF (294/362 Pages) Texas Instruments – Multicore DSP+ARM KeyStone II System-on-Chip (SoC)

TCI6636K2H
Multicore DSP+ARM KeyStone II System-on-Chip (SoC)
SPRS835F—October 2013
It should be assumed that any registers not included in these sections are not supported by the device. Furthermore,
only the bits within the registers described here are supported. Avoid writing to any reserved memory location or
changing the value of reserved bits.
The PLL Controller module as described in the Phase Locked Loop (PLL) Controller for KeyStone Devices User Guide
in 2.4 ‘‘Related Documentation from Texas Instruments’’ on page 19 includes a superset of features, some of which
are not supported on the TCI6636K2H device. The following sections describe the registers that are supported.
10.5.1 Main PLL Controller Device-Specific Information
10.5.1.1 Internal Clocks and Maximum Operating Frequencies
The Main PLL, used to drive theC66x CorePacs, the switch fabric, and a majority of the peripheral clocks (all but the
ARM CorePacs, DDR3, and the PASS modules) requires a PLL Controller to manage the various clock divisions,
gating, and synchronization. Unlike other PLL, CLKOD functionality of Main PLL is replaced by PLL controller
Post-Divider register (POSTDIV). The POSTDIV.RATIO[3:0] and POSTDIV.POSTDEN bits control the post
divider ratio and divider enable respectively. PLLM[5:0] input of the Main PLL is controlled by the PLL controller
PLLM register.
The Main PLL Controller has four SYSCLK outputs that are listed below, along with the clock descriptions. Each
SYSCLK has a corresponding divider that divides down the output clock of the PLL. Note that dividers are not
programmable unless explicitly mentioned in the description below.
• SYSCLK1: Full-rate clock for all C66x CorePacs. Using local dividers, SYSCLK1 is used to derive clocks
required for the majority of peripherals that do not need reset isolation.
The system peripherals and modules driven by SYSCLK1 are as follows; however, not all peripherals are
supported in every part. See the Features chapter for the complete list of peripherals supported in your part.
AIF2, BCP, FFTC, RAC, TAC, TCP3d, VCP2, EMIF16, USB 3.0, USIM, HyperLink, PCIe, SGMII, SRIO,
GPIO, Timer64, I²C, SPI, TeraNet, UART, ROM, CIC, Security Manager, BootCFG, PSC, Queue Manager,
Semaphore, MPUs, EDMA, MSMC, DDR3, EMIF.
• SYSCLK2: Full-rate, reset-isolated clock used to generate various other clocks required by peripherals that
need reset isolation: e.g., SmartReflex and SRIO.
• SYSCLK3: 1/x-rate clock used to clock the C66x CorePac emulation. The default rate for this clock is 1/3. This
clock is programmable from /1 to /32, where this clock does not violate the maximum of 350 MHz. SYSCLK3
can be turned off by software.
• SYSCLK4: 1/z-rate clock for the system trace module only. The default rate for this clock is 1/5. This clock is
configurable: the maximum configurable clock is 210 MHz and the minimum configuration clock is 32 MHz.
SYSCLK4 can be turned off by software.
Only SYSCLK3 and SYSCLK4 are programmable.
294 TCI6636K2H Peripheral Information and Electrical Specifications
Copyright 2013 Texas Instruments Incorporated
Submit Documentation Feedback