TCI6636K2H Datasheet, PDF (323/362 Pages) Texas Instruments – Multicore DSP+ARM KeyStone II System-on-Chip (SoC)

TCI6636K2H
Multicore DSP+ARM KeyStone II System-on-Chip (SoC)
SPRS835F—October 2013
Figure 10-37 SPI Master Mode Timing Diagrams — Base Timings for 3-Pin Mode
SPICLK
SPIDOUT
SPIDIN
1
2
3
4
MO(0)
78
MI(0)
5
MO(1)
MI(1)
MASTER MODE
POLARITY = 0 PHASE = 0
6
MO(n-1)
MI(n-1)
MO(n)
MI(n)
SPICLK
SPIDOUT
SPIDIN
4
MO(0)
78
MI(0)
5
6
MO(1)
MI(1)
MASTER MODE
POLARITY = 0 PHASE = 1
MO(n-1)
MI(n-1)
MO(n)
MI(n)
SPICLK
SPIDOUT
SPIDIN
4
5
MO(0)
7
8
MI(0)
MO(1)
MI(1)
MASTER MODE
POLARITY = 1 PHASE = 0
6
MO(n-1)
MI(n-1)
MO(n)
MI(n)
SPICLK
SPIDOUT
SPIDIN
4
MO(0)
78
MI(0)
5
6
MO(1)
MI(1)
MASTER MODE
POLARITY = 1 PHASE = 1
MO(n-1)
MI(n-1)
MO(n)
MI(n)
Figure 10-38 SPI Additional Timings for 4-Pin Master Mode with Chip Select Option
MASTER MODE 4 PIN WITH CHIP SELECT
19
20
SPICLK
SPIDOUT
SPIDIN
SPISCSx
MO(0)
MI(0)
MO(1)
MI(1)
MO(n-1)
MI(n-1)
MO(n)
MI(n)
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TCI6636K2H Peripheral Information and Electrical Specifications 323