TCI6636K2H Datasheet, PDF (328/362 Pages) Texas Instruments – Multicore DSP+ARM KeyStone II System-on-Chip (SoC)

TCI6636K2H
Multicore DSP+ARM KeyStone II System-on-Chip (SoC)
SPRS835F—October 2013
10.16 Security Accelerator
The Security Accelerator (SA) provides wire-speed processing on 1 Gbps Ethernet traffic on IPSec, SRTP, and
3GPP Air interface security protocols. It functions on the packet level with the packet and the associated security
context being one of the above three types. The Security Accelerator is coupled with the Network Coprocessor, and
receives the packet descriptor containing the security context in the buffer descriptor and the data to be
encrypted/decrypted in the linked buffer descriptor. For more information, see the Security Accelerator (SA) for
KeyStone Devices User Guide in 2.4 ‘‘Related Documentation from Texas Instruments’’ on page 19.
10.17 Network Coprocessor Gigabit Ethernet (GbE) Switch Subsystem
The gigabit Ethernet (GbE) switch subsystem provides an efficient interface between the device and the networked
community. The Ethernet Media Access Controller (EMAC) supports 10Base-T (10 Mbits/second), and 100BaseTX
(100 Mbps), in half- or full-duplex mode, and 1000BaseT (1000 Mbps) in full-duplex mode, with hardware flow
control and quality-of-service (QOS) support. The GbE switch subsystem is coupled with the Network Coprocessor.
For more information, see the Gigabit Ethernet (GbE) Switch Subsystem for KeyStone Devices User Guide in
2.4 ‘‘Related Documentation from Texas Instruments’’ on page 19.
An address range is assigned to the TCI6636K2H. Each individual device has a 48-bit MAC address and consumes
only one unique MAC address out of the range. There are two registers to hold these values, MACID1[31:0] (32 bits)
and MACID2[15:0] (16 bits) . The bits of these registers are defined as follows:
Figure 10-46 MACID1 Register (MMR Address 0x02620110)
31
0
MACID
R-xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx
Legend: R = Read only; -x, value is indeterminate
Table 10-47 MACID1 Register Field Descriptions
Bit
Field
Description
31-0 MAC ID
MAC ID. Lower 32 bits.
Figure 10-47 MACID2 Register (MMR Address 0x02620114)
31
24
23
CRC
Reserved
R+,cccc cccc
R-rr rrrr
Legend: R = Read only; -x, value is indeterminate
Table 10-48 MACID2 Register Field Descriptions (Part 1 of 2)
Bit
Field
Description
31-24 Reserved
Variable
23-18 Reserved
000000
17
FLOW
MAC Flow Control
0 = Off
1 = On
18
17
16
15
0
FLOW BCAST
MACID
R-z
R-y
R-xxxx xxxx xxxx xxxx
328 TCI6636K2H Peripheral Information and Electrical Specifications
Copyright 2013 Texas Instruments Incorporated
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