TCI6636K2H Datasheet, PDF (227/362 Pages) Texas Instruments – Multicore DSP+ARM KeyStone II System-on-Chip (SoC)

TCI6636K2H
Multicore DSP+ARM KeyStone II System-on-Chip (SoC)
SPRS835F—October 2013
8.1.2.4.5 I²C Boot Parameter Table
I
Table 8-21
I²C Boot Parameter Table
Offset Field
22 Option
24 Boot Dev Addr
26 Boot Dev Addr Ext
28 Broadcast Addr
30 Local Address
34 Bus Frequency
36 Next Dev Addr
38 Next Dev Addr Ext
40 Address Delay
End of Table 8-21
Value
Bits 02 - 00 Mode
000 = Boot Parameter Table Mode
001 = Boot Table Mode
010 = Boot Config Mode
011 = Load GP header format data
100 = Slave Receive Boot Config
Bits 15 - 03= Reserved
The I²C device address to boot from
Extended boot device address
I²C address used to send data in the I²C master broadcast mode.
The I²C address of this device
The desired I²C data rate (kHz)
The next device address to boot (Used only if boot config option is selected)
The extended next device address to boot (Used only if boot config option is selected)
The number of CPU cycles to delay between writing the address to an I²C EEPROM and
reading data.
Configured Through Boot
Configuration Pins
NO
YES
YES
NO
NO
NO
NO
NO
NO
8.1.2.4.6 SPI Boot Parameter Table
Table 8-22 SPI Boot Parameter Table
Byte Offset Name
22
Options
24
Address Width
26
NPin
28
Chipsel
30
Mode
32
C2Delay
34
Bus Freq, 100kHz
36
Read Addr MSW
38
Read Addr LSW
40
Next Chip Select
42
Next Read Addr MSW
44
Next Read Addr LSW
End of Table 8-22
Description
Bits 01 & 00 Modes
00 = Load a boot parameter table from the SPI (Default mode)
01 = Load boot records from the SPI (boot tables)
10 = Load boot config records from the SPI (boot config tables)
11 = Load GP header blob
Bits 15- 02= Reserved
The number of bytes in the SPI device address. Can be 16 or 24 bit
The operational mode, 4 or 5 pin
The chip select used (valid in 4 pin mode only). Can be 0-3.
Standard SPI mode (0-3)
Setup time between chip assert and transaction
The SPI bus frequency in kHz.
The first address to read from, MSW (valid for 24 bit address width only)
The first address to read from, LSW
Next Chip Select to be used (Used only in boot Config mode)
The Next read address (used in boot config mode only)
The Next read address (used in boot config mode only)
Configured Through Boot
Configuration Pins
NO
YES
YES
YES
YES
NO
NO
YES
YES
NO
NO
NO
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Device Boot and Configuration 227