TCI6636K2H Datasheet, PDF (53/362 Pages) Texas Instruments – Multicore DSP+ARM KeyStone II System-on-Chip (SoC)

TCI6636K2H
Multicore DSP+ARM KeyStone II System-on-Chip (SoC)
SPRS835F—October 2013
Table 5-2
Signal Name
PCIERXN0
PCIERXP0
PCIERXN1
PCIERXP1
PCIETXN0
PCIETXP0
PCIETXN1
PCIETXP1
PCIEREFRES
RIORXN0
RIORXP0
RIORXN1
RIORXP1
RIORXN2
RIORXP2
RIORXN3
RIORXP3
RIOTXN0
RIOTXP0
RIOTXN1
RIOTXP1
RIOTXN2
RIOTXP2
RIOTXN3
RIOTXP3
RIOREFRES
SGMII0RXN
SGMII0RXP
SGMII0TXN
SGMII0TXP
SGMII1RXN
SGMII1RXP
SGMII1TXN
SGMII1TXP
SGMII2RXN
SGMII2RXP
SGMII2TXN
SGMII2TXP
SGMII3RXN
SGMII3RXP
Terminal Functions — Signals and Control by Function (Part 16 of 19)
Ball No. Type IPD/IPU Description
PCIe
AU31 I
AU32 I
PCIexpress lane 0 receive data
AV30 I
AV31 I
PCIexpress lane 1 receive data
AT30 O
AT31 O
PCIexpress lane 0 transmit data
AR29 O
AR30 O
AM26 A
PCIexpress lane 1 transmit data
PCIexpress SerDes reference resistor input (3 kΩ +/- 1%)
Serial RapidIO
AV24 I
AV25 I
Serial RapidIO lane 0 receive data
AU22 I
AU23 I
Serial RapidIO lane 1 receive data
AW22 I
AW23 I
Serial RapidIO lane 2 receive data
AV21 I
AV22 I
Serial RapidIO lane 3 receive data
AT24 O
AT25 O
Serial RapidIO lane 0 transmit data
AR23 O
AR24 O
Serial RapidIO lane 1 transmit data
AP22 O
AP23 O
Serial RapidIO lane 2 transmit data
AT21 O
AT22 O
AM21 A
Serial RapidIO lane 3 transmit data
Serial RapidIO SerDes reference resistor input (3 kΩ +/- 1%)
SGMII
AW28 I
AW29 I
Ethernet MAC SGMII port 0 receive data
AU28 O
AU29 O
Ethernet MAC SGMII port 0 transmit data
AV27 I
AV28 I
Ethernet MAC SGMII port 1 receive data
AT27 O
AT28 O
Ethernet MAC SGMII port 1 transmit data
AU25 I
AU26 I
Ethernet MAC SGMII port 2 receive data
AR26 O
AR27 O
Ethernet MAC SGMII port 2 transmit data
AW25 I
AW26 I
Ethernet MAC SGMII port 3 receive data
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