TCI6636K2H Datasheet, PDF (223/362 Pages) Texas Instruments – Multicore DSP+ARM KeyStone II System-on-Chip (SoC)

TCI6636K2H
Multicore DSP+ARM KeyStone II System-on-Chip (SoC)
SPRS835F—October 2013
8.1.2.4 Boot Parameter Table
The ROM Bootloader (RBL) uses a set of tables to carry out the boot process. The boot parameter table is the most
common format the RBL employs to determine the boot flow. These boot parameter tables have certain parameters
common across all the boot modes, while the rest of the parameters are unique to the boot modes. The common
entries in the boot parameter table are shown in table Table 8-16.
Table 8-16 Boot Parameter Table Common Parameters
Byte
Offset Name
0
Length
2
Checksum
4
Boot Mode
6
Port Num
8
SW PLL, MSW
10
SW PLL, LSW
12
Sec PLL Config, MSW
14
Sec PLL Config, LSW
16
System Freq
18
Core Freq
20
Boot Master
End of Table 8-16
Description
The length of the table, including the length field, in bytes.
The 16 bits ones complement of the ones complement of the entire table. A value of 0 will disable checksum
verification of the table by the boot ROM.
Internal values used by RBL for different boot modes.
Identifies the device port number to boot from, if applicable
PLL configuration, MSW
PLL configuration, LSW
ARM PLL configuration, MSW
ARM PLL configuration, LSW
The Frequency of the system clock in MHz
The frequency of the core clock in MHz
Set to TRUE if C66x is the master core.
8.1.2.4.1 EMIF16 Boot Parameter Table
Table 8-17 EMIF16 Boot Parameter Table
Byte
Offset Name
22
Options
24
Type
26
Branch Address MSW
28
Branch Address LSW
30
Chip Select
32
Memory Width
34
Wait Enable
36
Async Config MSW
38
Async Config LSW
End of Table 8-17
Description
Async Config Parameters are used.
0 = Value in the async config paramters are not used to program async config
registers.
1 = Value in the async config paramters are used to program async config registers.
Set to 0 for EMIF16 (NOR) boot
Most significant bit for Branch address (depends on chip select)
Least significant bit for Branch address (depends on chip select)
Chip Select for the NOR flash
Memory width of the Emif16 bus (16 bits)
Extended wait mode enabled
0 = Wait enable is disabled
1 = Wait enable is enabled
Async Config Register MSW
Async Config Register LSW
Configured Through Boot
Configuration Pins
NO
NO
YES
YES
YES
YES
YES
NO
NO
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Device Boot and Configuration 223