TCI6636K2H Datasheet, PDF (190/362 Pages) Texas Instruments – Multicore DSP+ARM KeyStone II System-on-Chip (SoC)

TCI6636K2H
Multicore DSP+ARM KeyStone II System-on-Chip (SoC)
SPRS835F—October 2013
Figure 7-4 TeraNet C66x to SDMA
L2 Cache_0_A
L2 Cache_0_B
L2 Cache_1_A
L2 Cache_1_B
L2 Cache_2_A
L2 Cache_2_B
L2 Cache_3_A
L2 Cache_3_B
L2 Cache_4_A
L2 Cache_4_B
From TeraNet 3_A-2
TNet_3_M
CPU/3
TNet_3_N
CPU/3
TNet_3_O
CPU/3
TNet_3_P
CPU/3
TNet_3_Q
CPU/3
L2 Cache_5_A
L2 Cache_5_B
L2 Cache_6_A
L2 Cache_6_B
L2 Cache_7_A
L2 Cache_7_B
TNet_3_R
CPU/3
TNet_3_S
CPU/3
TNet_3_T
CPU/3
Tracer_L2_0
Tracer_L2_1
Tracer_L2_2
Tracer_L2_3
Tracer_L2_4
Tracer_L2_5
Tracer_L2_6
Tracer_L2_7
6636
S ^CorePac_0
S ^CorePac_1
S ^CorePac_2
S ^CorePac_3
S ^CorePac_4
S ^CorePac_5
S ^CorePac_6
S ^CorePac_7
190 System Interconnect
Copyright 2013 Texas Instruments Incorporated
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