TCI6636K2H Datasheet, PDF (11/362 Pages) Texas Instruments – Multicore DSP+ARM KeyStone II System-on-Chip (SoC)

List of Tables
Table 1-1
Table 2-1
Table 3-1
Table 3-2
Table 4-1
Table 5-1
Table 5-2
Table 5-3
Table 5-4
Table 5-5
Table 6-1
Table 6-2
Table 6-3
Table 6-4
Table 6-5
Table 6-6
Table 6-7
Table 6-8
Table 6-9
Table 6-10
Table 6-11
Table 6-12
Table 6-13
Table 6-14
Table 6-15
Table 6-16
Table 6-17
Table 6-18
Table 6-19
Table 6-20
TCI6636 Release History . . . . . . . . . . . . . . . . . . . . . .5
Characteristics of the TCI6636K2H Processor 15
Available Memory Page Protection Schemes 26
CorePac Revision ID Register (MM_REVID) Field
Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Cortex-A15 Processor Core Supported
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
I/O Functional Symbol Definitions . . . . . . . . . . 38
Terminal Functions — Signals and Control by
Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Terminal Functions — Power and Ground . . . 57
Terminal Functions — By Signal Name . . . . . . 59
Terminal Functions — By Ball Number . . . . . 67
Device Memory Map Summary for
TCI6636K2H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
MPU0-MPU5 Default Configuration . . . . . . . . . 93
MPU6-MPU11 Default Configuration . . . . . . . . 93
MPU12-MPU14 Default Configuration. . . . . . . 94
MPU Memory Regions . . . . . . . . . . . . . . . . . . . . . . 94
Master ID Settings . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Privilege ID Settings . . . . . . . . . . . . . . . . . . . . . . . . 97
MPU Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
Configuration Register Field Descriptions . . 100
Programmable Range n Start Address Register
Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . 101
MPU0-MPU5 Programmable Range n Start
Address Register (PROGn_MPSAR) Reset
Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
MPU6-MPU11 Programmable Range n Start
Address Register (PROGn_MPSAR) Reset
Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
MPU12-MPU14 Programmable Range n Start
Address Register (PROGn_MPSAR) Reset
Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
Programmable Range n End Address Register
Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . 103
MPU0-MPU5 Programmable Range n End
Address Register (PROGn_MPEAR) Reset
Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
MPU6-MPU11 Programmable Range n End
Address Register (PROGn_MPEAR) Reset
Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
MPU12-MPU14 Programmable Range n End
Address Register (PROGn_MPEAR) Reset
Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
Programmable Range n Memory Protection
Page Attribute Register Field Descriptions. . 104
MPU0-MPU5 Programmable Range n Memory
Protection Page Attribute Register
(PROGn_MPPAR) Reset Values . . . . . . . . . . . . . 106
MPU6-MPU11 Programmable Range n Memory
Protection Page Attribute Register
(PROGn_MPPAR) Reset Values . . . . . . . . . . . . . 107
TCI6636K2H
SPRS835F—February 2012—Revised October 2013
Table 6-21
Table 6-22
Table 6-23
Table 6-24
Table 6-25
Table 6-26
Table 6-27
Table 6-28
Table 6-29
Table 6-30
Table 6-31
Table 6-32
Table 6-33
Table 6-34
Table 6-35
Table 6-36
Table 6-37
Table 6-38
Table 7-1
Table 7-2
Table 7-3
Table 7-4
Table 7-5
Table 8-1
Table 8-2
Table 8-3
Table 8-4
Table 8-5
Table 8-6
Table 8-7
Table 8-8
Table 8-9
Table 8-10
Table 8-11
Table 8-12
Table 8-13
MPU12-MPU14 Programmable Range n
Memory Protection Page Attribute Register
(PROGn_MPPAR) Reset Values . . . . . . . . . . . . . .107
System Event Mapping — C66x CorePac Primary
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .110
System Event Mapping — ARM CorePac
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .113
CIC0 Event Inputs — C66x CorePac Secondary
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .124
CIC1 Event Inputs — C66x CorePac Secondary
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .135
CIC2 Event Inputs (Secondary Events for
EDMA3CC0 and HyperLinks). . . . . . . . . . . . . . . .146
CIC0 Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .157
CIC1 Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .163
CIC2 Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .169
IPC Generation Registers (IPCGRx) . . . . . . . . . .173
LRESET and NMI Decoding . . . . . . . . . . . . . . . . .174
EDMA3 Channel Controller Configuration. . .176
EDMA3 Transfer Controller Configuration . . .177
EDMA3CC0 Events for TCI6636K2H . . . . . . . . .177
EDMA3CC1 Events for TCI6636K2H . . . . . . . . .179
EDMA3CC2 Events for TCI6636K2H . . . . . . . . .181
EDMA3CC3 Events for TCI6636K2H . . . . . . . . .182
EDMA3CC4 Events for TCI6636K2H . . . . . . . . .184
Data Space Interconnect -Section 1 . . . . . . . . .191
Data Space Interconnect - Section 2 . . . . . . . .193
Configuration Space Interconnect -
Section 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .200
Configuration Space Interconnect -
Section 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .202
Configuration Space Interconnect -
Section 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .204
C66x DSP Boot RAM Memory Map . . . . . . . . . .207
ARM Boot RAM Memory Map . . . . . . . . . . . . . . .208
Boot Mode Pins: Boot Device Values . . . . . . . .211
Sleep Boot Configuration Field Descriptions 212
I²C Passive Mode Device Configuration Field
Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .213
I²C Master Mode Device Configuration Field
Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .214
SPI Device Configuration Field Descriptions .215
EMIF Boot Device Configuration Field
Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .216
NAND Boot Device Configuration Field
Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .217
Serial Rapid I/O Boot Device Configuration Field
Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .218
Ethernet (SGMII) Boot Device Configuration
Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . .219
PCIe Boot Device Configuration Field
Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .220
BAR Config / PCIe Window Sizes . . . . . . . . . . . .221
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and
other important disclaimers. PRODUCTION DATA.