TCI6636K2H Datasheet, PDF (320/362 Pages) Texas Instruments – Multicore DSP+ARM KeyStone II System-on-Chip (SoC)

TCI6636K2H
Multicore DSP+ARM KeyStone II System-on-Chip (SoC)
SPRS835F—October 2013
Figure 10-35 I²C Receive Timings
11
9
SDA
8
SCL
4
10
1
3
6
5
12
7
14
13
3
2
Stop
Start
Repeated
Start
Stop
Table 10-40 I²C Switching Characteristics ⁽¹⁾
(see Figure 10-36)
No.
Parameter
16 t_c(SCL)
Cycle time, SCL
17 t_{su(SCLH-SDAL)} Setup time, SCL high to SDA low (for a repeated START condition)
18
t_h(SDAL-SCLL)
Hold time, SDA low after SCL low (for a START and a repeated START
condition)
19 t_w(SCLL)
20 t_w(SCLH)
21 t_d(SDAV-SDLH)
22 t_v(SDLL-SDAV)
23 t_w(SDAH)
24 t_r(SDA)
25 t_r(SCL)
26 t_f(SDA)
27 t_f(SCL)
28 t_d(SCLH-SDAH)
C_p
End of Table 10-40
Pulse duration, SCL low
Pulse duration, SCL high
Delay time, SDA valid to SCL high
Valid time, SDA valid after SCL low (for I²C bus devices)
Pulse duration, SDA high between STOP and START conditions
Rise time, SDA
Rise time, SCL
Fall time, SDA
Fall time, SCL
Delay time, SCL high to SDA high (for STOP condition)
Capacitance for each I²C pin
1 C_b = total capacitance of one bus line in pF. If mixed with HS-mode devices, faster fall-times are allowed.
Standard Mode
Min
Max
10
4.7
Fast Mode
Min Max Unit
2.5
μs
0.6
μs
4
0.6
μs
4.7
1.3
μs
4
0.6
μs
250
100
ns
0
0
0.9 μs
4.7
1.3
μs
1000
1000
300
300
20 + 0.1C_b ⁽¹⁾
20 + 0.1C_b ⁽¹⁾
20 + 0.1C_b ⁽¹⁾
20 + 0.1C_b ⁽¹⁾
300 ns
300 ns
300 ns
300 ns
4
0.6
μs
10
10 pF
320 TCI6636K2H Peripheral Information and Electrical Specifications
Copyright 2013 Texas Instruments Incorporated
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