TCI6636K2H Datasheet, PDF (288/362 Pages) Texas Instruments – Multicore DSP+ARM KeyStone II System-on-Chip (SoC)

TCI6636K2H
Multicore DSP+ARM KeyStone II System-on-Chip (SoC)
SPRS835F—October 2013
The following sequence must be followed during a power-on reset:
1. Wait for all power supplies to reach normal operating conditions while keeping the POR pin asserted (driven
low). While POR is asserted, all pins except RESETSTAT will be set to high-impedance. After the POR pin is
deasserted (driven high), all Z group pins, low group pins, and high group pins are set to their reset state and
remain in their reset state until otherwise configured by their respective peripheral. All peripherals that are
power-managed are disabled after a power-on reset and must be enabled through the Device State Control
Registers (for more details, see 8.2.3 ‘‘Device State Control Registers’’ on page 234).
2. Clocks are reset, and they are propagated throughout the chip to reset any logic that was using reset
synchronously. All logic is now reset and RESETSTAT is driven low, indicating that the device is in reset.
3. POR must be held active until all supplies on the board are stable, and then for at least an additional period of
time (as specified in Section 10.2.1 ‘‘Power-Up Sequencing’’ on page 271) for the chip-level PLLs to lock.
4. The POR pin can now be de-asserted. Reset-sampled pin values are latched at this point. Then, all chip-level
PLLs are taken out of reset, locking sequences begin, and all power-on device initialization processes begin.
5. After device initialization is complete, the RESETSTAT pin is de-asserted (driven high). By this time, the
DDR3A PLL and DDR3B PLL have already completed their locking sequences and are supplying a valid clock.
The system clocks of the PLL controllers are allowed to finish their current cycles and then are paused for 10
cycles of their respective system reference clocks. After the pause, the system clocks are restarted at their
default divide-by settings.
6. The device is now out of reset and code execution begins as dictated by the selected boot mode.
Note—To most of the device, reset is de-asserted only when the POR and RESET pins are both de-asserted
(driven high). Therefore, in the sequence described above, if the RESET pin is held low past the low period
of the POR pin, most of the device will remain in reset. The RESET pin should not be tied to the POR pin.
10.4.2 Hard Reset
A hard reset will reset everything on the device except the PLLs, test logic, emulation logic, and reset-isolated
modules. POR should also remain de-asserted during this time.
Hard reset is initiated by the following:
• RESET pin
• RSCTRL Register in the PLL Controller
• Watchdog timer
• Emulation
By default, all the initiators listed above are configured to generate a hard reset. Except for emulation, all of the other
three initiators can be configured in the RSCFG Register in the PLL Controller to generate soft resets.
The following sequence must be followed during a hard reset:
1. The RESET pin is asserted (driven low) for a minimum of 24 CLKIN1 cycles. During this time the RESET
signal propagates to all modules (except those specifically mentioned above). To prevent off-chip contention
during the warm reset, all I/O must be Hi-Z for modules affected by RESET.
2. Once all logic is reset, RESETSTAT is asserted (driven low) to denote that the device is in reset.
3. The RESET pin can now be released. A minimal device initialization begins to occur. Note that configuration
pins are not re-latched and clocking is unaffected within the device.
288 TCI6636K2H Peripheral Information and Electrical Specifications
Copyright 2013 Texas Instruments Incorporated
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