TCI6636K2H Datasheet, PDF (94/362 Pages) Texas Instruments – Multicore DSP+ARM KeyStone II System-on-Chip (SoC)

TCI6636K2H
Multicore DSP+ARM KeyStone II System-on-Chip (SoC)
SPRS835F—October 2013
Table 6-4
MPU12-MPU14 Default Configuration
Setting
MPU12
SPI0
Default permission
Assume allowed
Number of allowed IDs supported
16
Number of programmable ranges supported 2
Compare width
End of Table 6-4
1KB granularity
MPU13
SPI1
Assume allowed
16
2
1KB granularity
MPU14
SPI2
Assume allowed
16
2
1KB granularity
Table 6-5
MPU Memory Regions
Memory Protection
MPU0
Main CFG SCR
MPU1
QM_SS DATA PORT
MPU2
QM_SS CFG1 PORT
MPU3
BCR
MPU4
RAC 0/1
MPU5
QM_SS CFG2 PORT
MPU6
Reserved
MPU7
DDR3B
MPU8
SPIROM/EMIF16
MPU9
INTC/AINTC
MPU10
Semaphore
MPU11
SCR_6 and CPU/6 CFG SCR
MPU12
SPI0
MPU13
SPI1
MPU14
SPI2
End of Table 6-5
Start Address
0x01D0_0000
0x23A0_0000
0x02A0_0000
0x027C_0000
0x0210_0000
0x02A0_4000
0x02C0_0000
0x2101_0000
0x20B0_0000
0x0264_0000
0x0260_0000
0x0220_0000
0x2100_0400
0x2100_0400
0x2100_0800
End Address
0x01E7_FFFF
0x23BF_FFFF
0x02AF_FFFF
0x027C_03FF
0x0215_FFFF
0x02BF_FFFF
0x02CD_FFFF
0xFFFF_FFFF
0x3FFF_FFFF
0x0264_07FF
0x0260_9FFF
0x03FF_FFFF
0x2100_07FF
0x2100_07FF
0x2100_0AFF
Table 6-6 shows the unique Master ID assigned to each C66x CorePac and peripherals on the device.
Table 6-6
Master ID
0
1
2
3
4
5
6
7
8
9
10
11
12
13
Master ID Settings (Part 1 of 4)
TCI6636K2H
C66x CorePac0 Data
C66x CorePac1 Data
C66x CorePac2 Data
C66x CorePac3 Data
C66x CorePac4 Data
C66x CorePac5 Data
C66x CorePac6 Data
C66x CorePac7 Data
ARM CorePac 0 non-cache accesses and cache accesses for all ARM cores
ARM CorePac 1 non-cache accesses
ARM CorePac 2 non-cache accesses
ARM CorePac 3 non-cache accesses
Reserved
Reserved
94 Memory, Interrupts, and EDMA for TCI6636K2H
Copyright 2013 Texas Instruments Incorporated
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