TCI6636K2H Datasheet, PDF (260/362 Pages) Texas Instruments – Multicore DSP+ARM KeyStone II System-on-Chip (SoC)

TCI6636K2H
Multicore DSP+ARM KeyStone II System-on-Chip (SoC)
SPRS835F—October 2013
Table 8-56 USB_PHY_CTL0 Register Field Descriptions (Part 2 of 2)
Bit
Field
1
UTMI_TXBITSTUFFENH
0
UTMI_TXBITSTUFFEN
End of Table 8-56
Description
High-byte Transmit Bit-Stuffing Enable
Function: controls bit stuffing on DATAINH[7:0] when OPMODE[1:0]=11b.
1 = Bit stuffing is enabled.
0 = Bit stuffing is disabled.
Low-byte Transmit Bit-Stuffing Enable
Function: controls bit stuffing on DATAIN[7:0] when OPMODE[1:0]=11b.
1 = Bit stuffing is enabled.
0 = Bit stuffing is disabled.
Figure 8-39
31
USB_PHY_CTL1 Register
Reserved
R-0
4
3
PIPE_TX2RX_LOOPBK
PIPE_EXT_PCLK_REQ
R/W-0
R/W-0
Legend: R = Read only; R/W = Read/Write, -n = value after reset
spacer
2
PIPE_ALT_CLK_SEL
R/W-0
6
5
PIPE_REF_CLKREQ_N
R-0
1
PIPE_ALT_CLK_REQ
R-0
0
PIPE_ALT_CLK_EN
R/W-0
Table 8-57 USB_PHY_CTL1 Register Field Descriptions
Bit Field
Description
31-6 Reserved
Reserved
5 PIPE_REF_CLKREQ_N Reference Clock Removal Acknowledge.
When the pipeP_power-down control into the PHY turns off the MPLL in the P3 state, PIPE_REF_CLKREQ_N is asserted
after the PLL is stable and the reference clock can be removed.
4 PIPE_TX2RX_LOOPBK Loop-back.
When this signal is asserted, data from the transmit predriver is looped back to the receiver slicers. LOS is bypassed and
based on the tx_en input so that rx_los=!tx_data_en.
3 PIPE_EXT_PCLK_REQ External PIPE Clock Enable Request.
When asserted, this signal enables the pipeP_pclk output regardless of power state (along with the associated increase
in power consumption).
2 PIPE_ALT_CLK_SEL Alternate Clock Source Select.
Selects the alternate clock sources instead of the internal MPLL outputs for the PCS clocks.
1 = Uses alternate clocks.
0 = Users internal MPLL clocks.
Change only during a reset.
1 PIPE_ALT_CLK_REQ Alternate Clock Source Request.
Indicates that the alternate clocks are needed by the slave PCS (that is, to boot the master MPLL). Connect to the
alt_clk_en on the master.
0 PIPE_ALT_CLK_EN Alternate Clock Enable.
Enables the ref_pcs_clk and ref_pipe_pclk output clocks (if necessary, powers up the MPLL).
End of Table 8-57
260 Device Boot and Configuration
Copyright 2013 Texas Instruments Incorporated
Submit Documentation Feedback