TCI6636K2H Datasheet, PDF (305/362 Pages) Texas Instruments – Multicore DSP+ARM KeyStone II System-on-Chip (SoC)

TCI6636K2H
Multicore DSP+ARM KeyStone II System-on-Chip (SoC)
SPRS835F—October 2013
Table 10-27 ARM PLL Control Register 0 Field Descriptions
Bit
Field
Description
31-24 BWADJ[7:0]
BWADJ[11:8] and BWADJ[7:0] are located inARMPLLCTL0 and ARMPLLCTL1 registers. BWADJ[11:0] should be
programmed to a value equal to half of PLLM[12:0] value (round down if PLLM has an odd value) Example: If PLLM = 15,
then BWADJ = 7
23
BYPASS
PLL bypass mode:
0 = PLL is not in BYPASS mode
1 = PLL is in BYPASS mode
22-19 CLKOD
A 4-bit field that selects the values for the PLL post divider. Valid post divider values are 1 and even values from 2 to 16.
CLKOD field is loaded with output divide value minus 1
18-6 PLLM
A 13-bit field that selects the values for the multiplication factor
5-0 PLLD
End of Table 10-27
A 6-bit field that selects the values for the reference divider
Figure 10-20 ARM PLL Control Register 1 (ARMPLLCTL1)
31
15
14
Reserved
PLLRST
RW - 00000000000000000
RW-0
Legend: RW = Read/Write; -n = value after reset
13
7
Reserved
RW-0000000
6
ENSAT
RW-0
5
4
Reserved
R-00
3
0
BWADJ[11:8]
RW- 0000
Table 10-28 ARM PLL Control Register 1Field Descriptions
Bit
Field
Description
31-15 Reserved
Reserved
14
PLLRST
PLL Reset bit
0 = PLL Reset is released
1 = PLL Reset is asserted
13-7 Reserved
Reserved
6
ENSAT
Needs to be set to 1 for proper PLL operation
5-4 Reserved
Reserved
3-0 BWADJ[11:8]
End of Table 10-28
BWADJ[11:8] and BWADJ[7:0] are located in ARMPLLCTL0 and ARMPLLCTL1 registers. BWADJ[11:0] should be
programmed to a value equal to half of PLLM[12:0] value (round down if PLLM has an odd value) Example: If PLLM = 15,
then BWADJ = 7
See the Phase Locked Loop (PLL) Controller for KeyStone Devices User Guide in 2.4 ‘‘Related Documentation from
Texas Instruments’’ on page 19 for the recommended programming sequence. Output Divide ratio and Bypass
enable/disable of the ARM PLL is also controlled by the SECCTL register in the PLL Controller. See the “PLL
Secondary Control Register (SECCTL)” on page 298 for more details.
10.5.5 Main PLL Controller/ARM/SRIO/HyperLink/PCIe/USB Clock Input Electrical Data/Timing
Table 10-29 Main PLL Controller/ARM/SRIO/HyperLink/PCIe/USB Clock Input Timing Requirements ⁽¹⁾ (Part 1 of 3)
(see Figure 10-21 through Figure 10-24)
No.
Min
Max
1 tc(SYSCLKN)
SYSCLK[P:N]
Cycle time SYSCLKN cycle time
3.25 or 6.51 or 8.138 ⁽²⁾
1 tc(SYSCLKP)
Cycle time SYSCLKP cycle time
3.25 or 6.51 or 8.138
3 tw(SYSCLKN)
Pulse width SYSCLKN high
0.45*tc
0.55*tc
2 tw(SYSCLKN)
Pulse width SYSCLKN low
0.45*tc
0.55*tc
Unit
ns
ns
ns
ns
Copyright 2013 Texas Instruments Incorporated
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TCI6636K2H Peripheral Information and Electrical Specifications 305