TCI6636K2H Datasheet, PDF (296/362 Pages) Texas Instruments – Multicore DSP+ARM KeyStone II System-on-Chip (SoC)

TCI6636K2H
Multicore DSP+ARM KeyStone II System-on-Chip (SoC)
SPRS835F—October 2013
Table 10-13 Main PLL Controller Module Clock Domains Internal and Shared Local Clock Dividers (Part 2 of 2)
Clock
Module
Internal Clock Divider(s) Shared Local Clock Divider
SYSCLK2 Internal Clock Dividers
Serial RapidIO (SRIO)
/3, /4, /6
--
SYSCLK2 SmartReflex C66x CorePacs
/12, /128
--
SmartReflex ARM CorePac
End of Table 10-13
/12, /128, /128
--
10.5.1.3 Module Clock Input
Table 10-7 lists various clock domains in the device and their distribution in each peripheral. The table also shows
the distributed clock division in modules and their mapping with source clocks of the device PLLs.
10.5.1.4 Main PLL Controller Operating Modes
The Main PLL Controller has two modes of operation: bypass mode and PLL mode. The mode of operation is
determined by the BYPASS bit of the PLL Secondary Control Register (SECCTL).
• In bypass mode, PLL input is fed directly out as SYSCLK1.
• In PLL mode, SYSCLK1 is generated from the PLL output using the values set in the PLLM and PLLD
fields in the MAINPLLCTL0 Register.
External hosts must avoid access attempts to the DSP while the frequency of its internal clocks is changing. User
software must implement a mechanism that causes the DSP to notify the host when the PLL configuration has
completed.
10.5.1.5 Main PLL Stabilization, Lock, and Reset Times
The PLL stabilization time is the amount of time that must be allotted for the internal PLL regulators to become
stable after device power-up. The device should not be taken out of reset until this stabilization time has elapsed.
The PLL reset time is the amount of wait time needed when resetting the PLL (writing PLLRST = 1), in order for the
PLL to properly reset, before bringing the PLL out of reset (writing PLLRST = 0). For the Main PLL reset time value,
see Table 10-14.
The PLL lock time is the amount of time needed from when the PLL is taken out of reset to when the PLL Controller
can be switched to PLL mode. The Main PLL lock time is given in Table 10-14.
Table 10-14 Main PLL Stabilization, Lock, and Reset Times
PLL stabilization time
PLL lock time
PLL reset time
End of Table 10-14
1 C = 1/SYSCLK1(N|P) cycle time in ns.
Parameter
Min
100
1000
Typ
Max Unit
μs
2000 × C ⁽¹⁾
ns
10.5.2 PLL Controller Memory Map
The memory map of the Main PLL Controller is shown in Table 10-15. TCI6636K2H-specific Main PLL Controller
Register definitions can be found in the sections following Table 10-15. For other registers in the table, see the Phase
Locked Loop (PLL) Controller for KeyStone Devices User Guide in 2.4 ‘‘Related Documentation from Texas
Instruments’’ on page 19.
296 TCI6636K2H Peripheral Information and Electrical Specifications
Copyright 2013 Texas Instruments Incorporated
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