TCI6636K2H Datasheet, PDF (322/362 Pages) Texas Instruments – Multicore DSP+ARM KeyStone II System-on-Chip (SoC)

TCI6636K2H
Multicore DSP+ARM KeyStone II System-on-Chip (SoC)
SPRS835F—October 2013
Table 10-42 SPI Switching Characteristics (Part 2 of 2)
(See Figure 10-37 and Figure 10-38)
No.
Parameter
Min
Max
Unit
4 td(SPIDOUT-SPC) Setup (Delay), initial data bit valid on SPIDOUT to initial edge on SPICLK
Polarity = 1, Phase = 1
5
ns
5 td(SPC-SPIDOUT) Setup (Delay), subsequent data bits valid on SPIDOUT to initial edge on
SPICLK. Polarity = 0 Phase = 0
2
ns
5 td(SPC-SPIDOUT) Setup (Delay), subsequent data bits valid on SPIDOUT to initial edge on
SPICLK Polarity = 0 Phase = 1
2
ns
5 td(SPC-SPIDOUT) Setup (Delay), subsequent data bits valid on SPIDOUT to initial edge on
SPICLK Polarity = 1 Phase = 0
2
ns
5 td(SPC-SPIDOUT) Setup (Delay), subsequent data bits valid on SPIDOUT to initial edge on
SPICLK Polarity = 1 Phase = 1
2
ns
6 toh(SPC-SPIDOUT) Output hold time, SPIDOUT valid after receive edge of SPICLK except for final
bit. Polarity = 0 Phase = 0
0.5*tc - 2
ns
6 toh(SPC-SPIDOUT) Output hold time, SPIDOUT valid after receive edge of SPICLK except for final
bit. Polarity = 0 Phase = 1
0.5*tc - 2
ns
6 toh(SPC-SPIDOUT) Output hold time, SPIDOUT valid after receive edge of SPICLK except for final
bit. Polarity = 1 Phase = 0
0.5*tc - 2
ns
6 toh(SPC-SPIDOUT) Output hold time, SPIDOUT valid after receive edge of SPICLK except for final
bit. Polarity = 1 Phase = 1
0.5*tc - 2
ns
Additional SPI Master Timings — 4 Pin Mode with Chip Select Option
19 td(SCS-SPC)
Delay from SPISCSx\ active to first SPICLK. Polarity = 0 Phase = 0
2*P2 - 5
2*P2 + 5 ns
19 td(SCS-SPC)
Delay from SPISCSx\ active to first SPICLK. Polarity = 0 Phase = 1
0.5*tc + (2*P2) - 5 0.5*tc + (2*P2) + 5 ns
19 td(SCS-SPC)
Delay from SPISCSx\ active to first SPICLK. Polarity = 1 Phase = 0
2*P2 - 5
2*P2 + 5 ns
19 td(SCS-SPC)
Delay from SPISCSx\ active to first SPICLK. Polarity = 1 Phase = 1
0.5*tc + (2*P2) - 5 0.5*tc + (2*P2) + 5 ns
20 td(SPC-SCS)
Delay from final SPICLK edge to master deasserting SPISCSx\.
Polarity = 0 Phase = 0
1*P2 - 5
1*P2 + 5 ^ns
20 td(SPC-SCS)
Delay from final SPICLK edge to master deasserting SPISCSx\.
Polarity = 0 Phase = 1
0.5*tc + (1*P2) - 5 0.5*tc + (1*P2) + 5 ^ns
20 td(SPC-SCS)
Delay from final SPICLK edge to master deasserting SPISCSx\.
Polarity = 1 Phase = 0
1*P2 - 5
1*P2 + 5 ^ns
20 td(SPC-SCS)
Delay from final SPICLK edge to master deasserting SPISCSx\.
Polarity = 1 Phase = 1
0.5*tc + (1*P2) - 5 0.5*tc + (1*P2) + 5 ^ns
tw(SCSH)
Minimum inactive time on SPISCSx\ pin between two transfers when
SPISCSx\ is not held using the CSHOLD feature.
2*P2 - 5
ns
End of Table 10-42
1 P2=1/(SYSCLK1/6)
322 TCI6636K2H Peripheral Information and Electrical Specifications
Copyright 2013 Texas Instruments Incorporated
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