TCI6636K2H Datasheet, PDF (302/362 Pages) Texas Instruments – Multicore DSP+ARM KeyStone II System-on-Chip (SoC)

TCI6636K2H
Multicore DSP+ARM KeyStone II System-on-Chip (SoC)
SPRS835F—October 2013
10.5.2.8 Reset Configuration Register (RSTCFG)
This register is used to configure the type of reset (a hard reset or a soft reset) initiated by RESET, the watchdog
timer, and the Main PLL Controller’s RSTCTRL Register. By default, these resets are hard resets. The Reset
Configuration Register (RSTCFG) is shown in Figure 10-15 and described in Table 10-23.
Figure 10-15 Reset Configuration Register (RSTCFG)
31
14
13
12
11
4
3
0
Reserved
PLLCTLRSTTYPE RESETTYPE
Reserved
WDTYPE[N ⁽¹⁾]
R-0x000000
R/W-0 ⁽²⁾
R/W-0²
R-0x0
R/W-0x00²
Legend: R = Read only; R/W = Read/Write; -n = value after reset
1 Where N = 1, 2, 3,....N (Not all these outputs may be used on a specific device.)
2 Writes are conditional based on valid key. For details, see Section 10.5.2.7 ‘‘Reset Control Register (RSTCTRL)’’.
Table 10-23 Reset Configuration Register Field Descriptions
Bit Field
Description
31-14 Reserved
Reserved
13 PLLCTLRSTTYPE PLL controller initiates a software-driven reset of type:
0 = Hard reset (default)
1 = Soft reset
12 RESETTYPE
RESET initiates a reset of type:
0 = Hard reset (default)
1 = Soft reset
11-4 Reserved
Reserved
3
WDTYPE3
2
WDTYPE2
1
WDTYPE1
0
WDTYPE0
End of Table 10-23
Watchdog timer [N] initiates a reset of type:
0 = Hard reset (default)
1 = Soft reset
10.5.2.9 Reset Isolation Register (RSISO)
This register is used to select the module clocks that must maintain their clocking without pausing through
non-power-on reset. Setting any of these bits effectively blocks reset to all Main PLL Control Registers in order to
maintain current values of PLL multiplier, divide ratios, and other settings. Along with setting the module-specific
bit in RSISO, the corresponding MDCTLx[12] bit also needs to be set in the PSC to reset-isolate a particular module.
For more information on the MDCTLx Register, see the Power Sleep Controller (PSC) for KeyStone Devices User
Guide in 2.4 ‘‘Related Documentation from Texas Instruments’’ on page 19. The Reset Isolation Register (RSISO)
is shown in Figure 10-16 and described in Table 10-24.
Figure 10-16 Reset Isolation Register (RSISO)
31
16
15
10
9
8
7
4
3
2
0
Reserved
R-0x0000
Reserved
R-0x00
SRIOISO
R/W-0
SRISO
R/W-0
Reserved
R-0x0
AIF2ISO
R/W-0
Reserved
R-000
Legend: R = Read only; R/W = Read/Write; -n = value after reset
302 TCI6636K2H Peripheral Information and Electrical Specifications
Copyright 2013 Texas Instruments Incorporated
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