TCI6636K2H Datasheet, PDF (24/362 Pages) Texas Instruments – Multicore DSP+ARM KeyStone II System-on-Chip (SoC)

TCI6636K2H
Multicore DSP+ARM KeyStone II System-on-Chip (SoC)
SPRS835F—October 2013
3.1.3 L2 Memory
The L2 memory configuration for the TCI6636K2H device is as follows:
• Total memory size is 8192KB
• Each CorePac contains 1024KB of memory
• Local starting address for each CorePac is 0080 0000h
L2 memory can be configured as all SRAM, all 4-way set-associative cache, or a mix of the two. The amount of L2
memory that is configured as cache is controlled through the L2MODE field of the L2 Configuration Register
(L2CFG) of the C66x CorePac. Figure 3-4 shows the available SRAM/cache configurations for L2. By default, L2 is
configured as all SRAM after device reset.
Figure 3-4 L2 Memory Configurations
L2 Mode Bits
000
001
010
011
100
101
110
L2 Memory
Block Base
Address
0080 0000h
1/2
SRAM
ALL
SRAM
31/32
SRAM
15/16
SRAM
7/8
SRAM
3/4
SRAM
4-Way
Cache
4-Way
Cache
4-Way
Cache
4-Way
Cache
4-Way
Cache
4-Way
Cache
512K bytes
0088 0000h
256K bytes
128K bytes
64K bytes
32K bytes
32K bytes
008C 0000h
008E 0000h
008F 0000h
008F 8000h
008F FFFFh
24 C66x CorePac
Copyright 2013 Texas Instruments Incorporated
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