TCI6636K2H Datasheet, PDF (177/362 Pages) Texas Instruments – Multicore DSP+ARM KeyStone II System-on-Chip (SoC)

TCI6636K2H
Multicore DSP+ARM KeyStone II System-on-Chip (SoC)
SPRS835F—October 2013
6.4.3 EDMA3 Transfer Controller Configuration
Each transfer controller on the device is designed differently based on considerations like performance
requirements, system topology (like main TeraNet bus width, external memory bus width), etc. The parameters that
determine the transfer controller configurations are:
• FIFOSIZE: Determines the size in bytes for the data FIFO that is the temporary buffer for the in-flight data.
The data FIFO is where the read return data read by the TC read controller from the source endpoint is stored
and subsequently written out to the destination endpoint by the TC write controller.
• BUSWIDTH: The width of the read and write data buses in bytes, for the TC read and write controller,
respectively. This is typically equal to the bus width of the main TeraNet interface.
• Default Burst Size (DBS): The DBS is the maximum number of bytes per read/write command issued by a
transfer controller.
• DSTREGDEPTH: This determines the number of destination FIFO register sets. The number of destination
FIFO register sets for a transfer controller determines the maximum number of outstanding transfer requests.
All four parameters listed above are fixed by the design of the device.
Table 6-33 shows the configuration of each of the EDMA3 transfer controllers present on the device.
Table 6-33 EDMA3 Transfer Controller Configuration
EDMA3 CC0/CC4
EDMA3 CC1
EDMA3 CC2
EDMA3CC3
Parameter
TC0
TC1
TC0
TC1
TC2
TC3
TC0
TC1
TC2
TC3
TC0
TC1
FIFOSIZE
1024
bytes
1024
bytes
1024
bytes
1024
bytes
1024
bytes
1024
bytes
1024
bytes
1024
bytes
1024
bytes
1024
bytes
1024
bytes
1024
bytes
BUSWIDTH
32 bytes 32 bytes 16 bytes 16 bytes 16 bytes 16 bytes 16 bytes 16 bytes 16 bytes 16 bytes 16 bytes 16 bytes
DSTREGDEPTH 4 entries 4 entries 4 entries 4 entries 4 entries 4 entries 4 entries 4 entries 4 entries 4 entries 4 entries 4 entries
DBS
128
bytes
End of Table 6-33
128
bytes
128
bytes
128
bytes
128
bytes
128
bytes
128
bytes
128
bytes
128
bytes
128
bytes
64 bytes 64 bytes
6.4.4 EDMA3 Channel Synchronization Events
The EDMA3 supports up to 64 DMA channels for all EDMA3CC that can be used to service system peripherals and
to move data between system memories. DMA channels can be triggered by synchronization events generated by
system peripherals. The following tables list the source of the synchronization event associated with each of the
EDMA EDMA3CC DMA channels. On the TCI6636K2H, the association of each synchronization event and DMA
channel is fixed and cannot be reprogrammed.
For more detailed information on the EDMA3 module and how EDMA3 events are enabled, captured, processed,
prioritized, linked, chained, and cleared, etc., see the Enhanced Direct Memory Access 3 (EDMA3) for KeyStone
Devices User Guide in 2.4 ‘‘Related Documentation from Texas Instruments’’ on page 19.
Table 6-34 EDMA3CC0 Events for TCI6636K2H (Part 1 of 3)
Event No. Event Name
Description
0
TIMER_8_INTL
Timer interrupt low
1
TIMER_8_INTH
Timer interrupt high
2
TIMER_9_INTL
Timer interrupt low
3
TIMER_9_INTH
Timer interrupt high
4
TIMER_10_INTL
Timer interrupt low
5
TIMER_10_INTH
Timer interrupt high
6
TIMER_11_INTL
Timer interrupt low
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