TCI6636K2H Datasheet, PDF (224/362 Pages) Texas Instruments – Multicore DSP+ARM KeyStone II System-on-Chip (SoC)

TCI6636K2H
Multicore DSP+ARM KeyStone II System-on-Chip (SoC)
SPRS835F—October 2013
8.1.2.4.2 SRIO Boot Parameter Table
Table 8-18 SRIO Boot Parameter Table
Byte Offset Name
Description
22
Options
Bit 0 Tx enable
0 = SRIO Transmit disable
1 = SRIO Transmit Enable
Bit 1 Mailbox Enable
0 = Mailbox mode disabled. (SRIO boot is in DirectIO mode).
1 = Mailbox mode enabled. (SRIO boot is in Messaging mode).
Bit 2 Bypass Configuration
0 = Configure the SRIO
1 = Bypass SRIO configuration
Bit 3 Bypass QM Configuration
0 = Configure the QM and CPDMA
1 = Bypass the QM and CPDMA configuration
Bit 4 PLL setup
0 = SERDES Configuration registers are taken without modification.
1 = SERDES Configuration are modified based on the reference clock and link
rate.
Bit 5-15 = Reserved
24
Lane Setup
0b0000 = SRIO configured as four 1x ports
0b0001 = SRIO configured as 3 ports (2x, 1x, 1x)
0b0010 = SRIO configured as 3 ports (1x, 1x, 2x)
0b0011 =SRIO configured as 2 ports (2x, 2x)
0b0100 = SRIO configured as 1 4x port
0b 0101 - 0bffff = Reserved
26
Reserved
Reserved
28
Node ID
The node ID value to set for this device
30
SerDes ref clk
The SerDes reference clock frequency, in 1/100 MHZ
32
Link Rate
Link rate, MHz
34
PF Low
Packet forward address range, low value
36
PF High
Packet Forward address range, high value
38
Promiscuous Mask The bit is set for each lane/port that is configured as promiscuous
40
Timeout Sec
Number of seconds before timeout. The value 0 disables the timeout
44
SERDES Aux, MSW
SERDES Auxillary Register Configuration, MSW
48
SERDES Aux, LSW
SERDES Auxillary Register Configuration, LSW
52
SERDES Rx Lane0 MSW SERDES Rx Configuration, Lane0, MSW
56
SERDES Rx Lane0 LSW SERDES Rx Configuration, Lane0, LSW
60
SERDES Rx Lane1 MSW SERDES Rx Configuration, Lane1, MSW
64
SERDES Rx Lane1 LSW SERDES Rx Configuration, Lane1, LSW
68
SERDES Rx Lane2 MSW SERDES Rx Configuration, Lane2, MSW
72
SERDES Rx Lane2 LSW SERDES Rx Configuration, Lane2, LSW
76
SERDES Rx Lane3 MSW SERDES Rx Configuration, Lane3, MSW
80
SERDES Rx Lane3 LSW SERDES Rx Configuration, Lane3, LSW
End of Table 8-18
Configured Through
Boot Configuration Pins
NO
YES (but not all lane setup
are possible through the
boot configuration pins)
NA
NO
YES
YES
NO
NO
NO
NO
NO
NO
NO
NO
NO
NO
NO
NO
NO
NO
224 Device Boot and Configuration
Copyright 2013 Texas Instruments Incorporated
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