TCI6636K2H Datasheet, PDF (27/362 Pages) Texas Instruments – Multicore DSP+ARM KeyStone II System-on-Chip (SoC)

TCI6636K2H
Multicore DSP+ARM KeyStone II System-on-Chip (SoC)
SPRS835F—October 2013
3.4 Power-Down Control
The C66x CorePac supports the ability to power-down various parts of the CorePac. The power-down controller
(PDC) of the CorePac can be used to power down L1P, the cache control hardware, the DSP, and the entire CorePac.
These power-down features can be used to design systems for lower overall system power requirements.
Note—The TCI6636K2H does not support power-down modes for the L2 memory at this time.
More information on the power-down features of the C66x CorePac can be found in the C66x CorePac Reference
Guide in 2.4 ‘‘Related Documentation from Texas Instruments’’ on page 19
3.5 C66x CorePac Revision
The version and revision of the C66x CorePac can be read from the CorePac Revision ID Register (MM_REVID)
located at address 0181 2000h. The MM_REVID register is shown in Table 3-2 and described in Table 3-2. The C66x
CorePac revision is dependent on the silicon revision being used.
Figure 3-5 CorePac Revision ID Register (MM_REVID)
31
16
15
0
VERSION
REVISION
R-n
R-n
Legend: R = Read only; R/W = Read/Write; -n = value after reset
Table 3-2
CorePac Revision ID Register (MM_REVID) Field Descriptions
Bit Name
Value
Description
31-16 VERSION
xxxxh
Version of the C66x CorePac implemented on the device will depend on the silicon being used.
15-0 REVISION
End of Table 3-2
0000h
Revision of the C66x CorePac version implemented on this device.
3.6 C66x CorePac Register Descriptions
See the C66x CorePac User Guide in 2.4 ‘‘Related Documentation from Texas Instruments’’ on page 19 for register
offsets and definitions.
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