TCI6636K2H Datasheet, PDF (289/362 Pages) Texas Instruments – Multicore DSP+ARM KeyStone II System-on-Chip (SoC)

TCI6636K2H
Multicore DSP+ARM KeyStone II System-on-Chip (SoC)
SPRS835F—October 2013
4. After device initialization is complete, the RESETSTAT pin is de-asserted (driven high).
Note—The POR pin should be held inactive (high) throughout the warm reset sequence. Otherwise, if POR
is activated (brought low), the minimum POR pulse width must be met. The RESET pin should not be tied
to the POR pin.
10.4.3 Soft Reset
A soft reset behaves like a hard reset except that the EMIF16 MMRs, DDR3A EMIF MMRs, DDR3B EMIF MMRs,
PCIe MMRs sticky bits, and external memory content are retained. POR should also remain de-asserted during this
time.
Soft reset is initiated by the following:
• RESET pin
• RSCTRL Register in the PLL Controller
• Watchdog timer
In the case of a soft reset, the clock logic and the power control logic of the peripherals are not affected, and,
therefore, the enabled/disabled state of the peripherals is not affected. On a soft reset, the DDR3A and DDR3B
memory controller registers are not reset. If the user places the DDR3A and DDR3B SDRAM in self-refresh mode
before invoking the soft reset, the DDR3A and DDR3B SDRAM memory content is retained.
During a soft reset, the following occurs:
1. The RESETSTAT pin goes low to indicate an internal reset is being generated. The reset propagates through
the system. Internal system clocks are not affected. PLLs remain locked.
2. After device initialization is complete, the RESETSTAT pin is deasserted (driven high). In addition, the PLL
Controller pauses system clocks for approximately 8 cycles.
At this point:
› The peripherals remain in the state they were in before the soft reset.
› The states of the Boot Mode configuration pins are preserved as controlled by the DEVSTAT Register.
› The DDR3A and DDR3B MMRs and PCIe MMRs retain their previous values. Only the DDR3A and
DDR3B memory controller and PCIe state machines are reset by the soft reset.
› The PLL Controller remains in the mode it was in prior to the soft reset.
› System clocks are unaffected.
The boot sequence is started after the system clocks are restarted. Because the Boot Mode configuration pins are not
latched with a soft reset, the previous values (as shown in the DEVSTAT Register), are used to select the boot mode.
10.4.4 Local Reset
The local reset can be used to reset a particular C66x CorePac without resetting any other device components.
Local reset is initiated by the following:
• LRESET pin
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TCI6636K2H Peripheral Information and Electrical Specifications 289