TCI6636K2H Datasheet, PDF (100/362 Pages) Texas Instruments – Multicore DSP+ARM KeyStone II System-on-Chip (SoC)

TCI6636K2H
Multicore DSP+ARM KeyStone II System-on-Chip (SoC)
SPRS835F—October 2013
6.2.1.2 Device-Specific MPU Registers
6.2.1.2.1 Configuration Register (CONFIG)
The configuration register (CONFIG) contains the configuration value of the MPU.
Figure 6-1 Configuration Register (CONFIG)
31
24
23
20
19
16
15
12
ADDR_WIDTH
NUM_FIXED
NUM_PROG
NUM_AIDS
MPU0
R-0
R-0
R-16
R-16
MPU1
R-0
R-0
R-16
R-16
MPU2
R-0
R-0
R-16
R-16
MPU3
R-0
R-0
R-2
R-16
MPU4
R-0
R-0
R-4
R-16
MPU5
R-0
R-0
R-16
R-16
MPU6
Reserved
Reset Values MPU7
R-0
R-0
R-16
R-16
MPU8
R-0
R-0
R-8
R-16
MPU9
R-0
R-0
R-4
R-16
MPU10
R-0
R-0
R-2
R-16
MPU11
R-0
R-0
R-16
R-16
MPU12
R-0
R-0
R-2
R-16
MPU13
R-0
R-0
R-2
R-16
MPU14
R-0
R-0
R-2
R-16
Legend: R = Read only; -n = value after reset
11 1
Reserved
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
0
ASSUME_ALLOWED
R-1
R-1
R-1
R-1
R-1
R-1
R-1
R-1
R-1
R-1
R-1
R-1
R-1
R-1
Table 6-9
Configuration Register Field Descriptions
Bits
Field
Description
31 – 24 ADDR_WIDTH
Address alignment for range checking
0 = 1KB alignment
6 = 64KB alignment
23 – 20 NUM_FIXED
Number of fixed address ranges
19 – 16 NUM_PROG
Number of programmable address ranges
15 – 12 NUM_AIDS
Number of supported AIDs
11 – 1 Reserved
Reserved. Always read as 0.
0
ASSUME_ALLOWED
End of Table 6-9
Assume allowed bit. When an address is not covered by any MPU protection range, this bit determines whether the
transfer is assumed to be allowed or not.
0 = Assume disallowed
1 = Assume allowed
6.2.2 MPU Programmable Range Registers
6.2.2.1 Programmable Range n Start Address Register (PROGn_MPSAR)
The Programmable Address Start Register holds the start address for the range. This register is writeable by a
supervisor entity only. If NS = 0 (non-secure mode) in the associated MPPAR register, then the register is also
writeable only by a secure entity.
100 Memory, Interrupts, and EDMA for TCI6636K2H
Copyright 2013 Texas Instruments Incorporated
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