TCI6636K2H Datasheet, PDF (93/362 Pages) Texas Instruments – Multicore DSP+ARM KeyStone II System-on-Chip (SoC)

TCI6636K2H
Multicore DSP+ARM KeyStone II System-on-Chip (SoC)
SPRS835F—October 2013
4 This region is mapped to DDR3A or DDR3B depending on the state of DDR3A_REMAP_EN pin at boot time. If the pin is ‘1’, this region is mapped to the first 2GB of DDR3A which
is aliased of 08 0000 0000 to 08 7FFF FFFF. If the pin is ‘0’, this region is mapped as 2GB of DDR3B.
5 MPAX from SES port extends the address to this region.
6 This region is aliased to 00 2101 0000-00 2101 01FF.
7 Access to 40-bit address requires XMC MPAX programmation.
8 Access to 40-bit address requires MSMC MPAX programmation. MPAX from SES port need to re-map the region of 00 2101 0000-00 2101 01FF to this region.
6.2 Memory Protection Unit (MPU)
CFG (configuration) space of all slave devices on the TeraNet is protected by the MPU. The TCI6636K2H contains
fifteen MPUs:
• MPU0 is used for main TeraNet_3P_B (SCR_3P (B)) CFG.
• MPU1/2/5 are used for QM_SS (one for VBUSM port and one each for the two configuration VBUSP ports).
• MPU3/4/6 are used for RAC_0/RAC_1 and one for BCR.
• MPU7 is used for DDR3_B.
• MPU8 is used for EMIF16.
• MPU9 is used for interrupt controllers connected to TeraNet_3P (SCR_3P).
• MPU10 is used for semaphore.
• MPU11 is used to protect TeraNet_6P_B (SCR_6P (B)) CPU/6 CFG TeraNet
• MPU12/13/14 are used for SPI0/1/2
This section contains MPU register map and details of device-specific MPU registers only. For MPU features and
details of generic MPU registers, see the Memory Protection Unit (MPU) for KeyStone Devices User Guide in
2.4 ‘‘Related Documentation from Texas Instruments’’ on page 19.
The following tables show the configuration of each MPU and the memory regions protected by each MPU.
Table 6-2
MPU0-MPU5 Default Configuration
Setting
Default permission
Number of allowed IDs
supported
Number of programmable
ranges supported
Compare width
End of Table 6-2
MPU0
Main SCR_3P
(B)
MPU1
(QM_SS DATA PORT)
Assume allowed Assume allowed
16
16
16
16
1KB granularity 1KB granularity
MPU2
(QM_SS CFG1
PORT)
Assume allowed
16
16
1KB granularity
MPU3
BCR CFG
MPU4
RAC 0/1
MPU5
(QM_SS CFG2
PORT)
Assume allowed Assume allowed Assume allowed
16
16
16
2
4
16
1KB granularity 1KB granularity 1KB granularity
Table 6-3
MPU6-MPU11 Default Configuration
Setting
MPU6
MPU7
DDR3B
Default permission
Reserved
Assume allowed
Number of allowed IDs
16
supported
Number of programmable
16
ranges supported
Compare width
End of Table 6-3
1KB granularity
MPU8
EMIF16
Assume allowed
16
8
1KB granularity
MPU9
INTC
MPU10
SM
MPU11
SCR_6P (B)
Assume allowed Assume allowed Assume allowed
16
16
16
4
2
16
1KB granularity 1KB granularity 1KB granularity
Copyright 2013 Texas Instruments Incorporated
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Memory, Interrupts, and EDMA for TCI6636K2H 93