TCI6636K2H Datasheet, PDF (225/362 Pages) Texas Instruments – Multicore DSP+ARM KeyStone II System-on-Chip (SoC)

TCI6636K2H
Multicore DSP+ARM KeyStone II System-on-Chip (SoC)
SPRS835F—October 2013
8.1.2.4.3 Ethernet Boot Parameter Table
Table 8-19 Ethernet Boot Parameter Table (Part 1 of 2)
Byte Offset
22
Name
Options
24
MAC High
26
MAC Med
28
MAC Low
30
Multi MAC High
32
Multi MAC Med
34
Multi MAC Low
36
Source Port
38
Dest Port
40
Device ID 12
42
Device ID 34
44
Dest MAC High
46
Dest MAC Med
48
Dest MAC Low
50
Lane Enable
52
SGMII Config
54
SGMII Control
56
SGMII Adv Ability
58
SGMII TX Cfg High
60
SGMII TX Cfg Low
62
SGMII RX Cfg High
64
SGMII RX Cfg Low
66
SGMII Aux Cfg High
68
SGMII Aux Cfg Low
Description
Configured Through Boot
Configuration Pins
Bits 02 - 00 Interface
NO
000 - 100 = Reserved
101 = SGMII
110 = Reserved
111 = Reserved
Bits 03 HD
0 = Half Duplex
1 = Full Duplex
Bit 4 Skip TX
0 = Send Ethernet Ready Frame every 3 seconds
1 = Don't send Ethernet Ready Frame
Bits 06 - 05 Initialize Config
00 = Switch, SerDes, SGMII and PASS are configured
01 = Initialization is not done for the peripherals that are already enabled
and running.
10 = Reserved
11 = None of the Ethernet system is configured.
Bits 15 - 07 Reserved
The 16 MSBs of the MAC address to receive during boot
NO
The 16 middle bits of the MAC address to receive during boot
NO
The 16 LSBs of the MAC address to receive during boot
NO
The 16 MSBs of the multi-cast MAC address to receive during boot
NO
The 16 middle bits of the multi-cast MAC address to receive during boot NO
The 16 LSBs of the multi-cast MAC address to receive during boot
NO
The source UDP port to accept boot packets from.
NO
A value of 0 will accept packets from any UDP port
The destination port to accept boot packets on.
NO
The first two bytes of the device ID.
NO
This is typically a string value, and is sent in the Ethernet ready frame
The 2nd two bytes of the device ID.
NO
The 16 MSBs of the MAC destination address used
NO
for the Ethernet ready frame. Default is broadcast.
The 16 middle bits of the MAC destination address
NO
The 16 LSBs of the MAC destination address
NO
One bit per lane.
0 - Lane disabled
1 - Lane enabled
Bits 0-3 are the config index, bit 4 set if direct config used, bit 5 set if no NO
configuration done
The SGMII control register value
NO
The SGMII ADV Ability register value
NO
The 16 MSBs of the SGMII Tx config register
NO
The 16 LSBs of the SGMII Tx config register
NO
The 16 MSBs of the SGMII Rx config register
NO
The 16 LSBs of the SGMII Rx config register
NO
The 16 MSBs of the SGMII Aux config register
NO
The 16 LSBs of the SGMII Aux config register
NO
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Device Boot and Configuration 225