TCI6636K2H Datasheet, PDF (219/362 Pages) Texas Instruments – Multicore DSP+ARM KeyStone II System-on-Chip (SoC)

TCI6636K2H
Multicore DSP+ARM KeyStone II System-on-Chip (SoC)
SPRS835F—October 2013
8.1.2.3 Ethernet (SGMII) Boot Device Configuration
Figure 8-9 Ethernet (SGMII) Boot Device Configuration Fields
DEVSTAT Boot Mode Pins ROM Mapping
16
15 14 13 12 11 10 9
8
765
Pa clk
Ref Clock
Ext Con
Lane Setup
Boot Master=1
Sys PLL Cfg
Pa clk
Ref Clock
Ext Con
ARM PLL Cfg
Boot Master=0
Sys PLL Cfg
4 321
Min
101
Min
101
0
Lendian
Lendian
Table 8-11 Ethernet (SGMII) Boot Device Configuration Field Descriptions
Bit
Field
Description
16
Pa clk
PA clock reference
0 = PA clocked at the same reference as the core reference
1 = PA clocked at the same reference as the SerDes reference (default)
15-14 Ref Clock
SRIO Reference clock frequency
0 = 125MHz
1 = 156.25MHz (default)
2 = Reserved
3 = Reserved
13-12 Ext Con
External connection mode
0 = MAC to MAC connection, master with auto negotiation
1 = MAC to MAC connection, slave with auto negotiation (default)
2 = MAC to MAC, forced link, maximum speed
3 = MAC to fiber connection
11-9 Lane Setup/ARM PLL
Setting
When Boot Master =0 (ARM is Boot Master), pin[11:9] used as ARM PLL Setting. The PLL default settings are
determined by the [11:9] bits. This will set the PLL to the maximum clock setting for the device. Table 8-27 shows
settings for various input clock frequencies.
When Boot Master =1 (C66x is Boot Master), pin [10:9] are used as Lane Set up.
0 = All SGMII ports enabled (default)
1 = Only SGMII port 0 enabled
2 = SGMII port 0 and 1 enabled
3 = SGMII port 0, 1 and 2 enabled
4-7 = Reserved
8
Boot Master
Boot Master select
0 = ARM is boot master (default)
1 = C66x is boot master
7-5
SYS PLL Setting
The PLL default settings are determined by the [7:5] bits. This will set the PLL to the maximum clock setting for the
device. Default system reference clock is 156.25 MHz. Table 8-27 shows settings for various input clock
frequencies. (default = 4)
4
Min
Minimum boot configuration select bit.
0 = Minimum boot pin select disabled
1 = Minimum boot pin select enabled.
When Min = 1, a predetermined set of values is configured (see the Device Configuration Field Descriptions table
for configuration bits with a "(default)" tag added in the description column).
When Min = 0, all fields must be independently configured.
3-1
Boot Devices
Boot Devices
101 = Ethernet boot mode
Others = Other boot modes
0
Lendian
End of Table 8-11
Endianess
0 = Big endian
1 = Little endian
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