TCI6636K2H Datasheet, PDF (213/362 Pages) Texas Instruments – Multicore DSP+ARM KeyStone II System-on-Chip (SoC)

TCI6636K2H
Multicore DSP+ARM KeyStone II System-on-Chip (SoC)
SPRS835F—October 2013
8.1.2.2.2 I²C Boot Device Configuration
I²C Passive Mode
In passive mode, the device does not drive the clock, but simply acks data received on the specified address.
Figure 8-3
I²C Passive Mode Device Configuration Fields
DEVSTAT Boot Mode Pins ROM Mapping
16 15 14 13 12 11 10
9
8
7
6
5
4
321
0
Slave Addr 1
Port
ARM PLL Cfg
Boot
Master
Sys PLL Config
Min
000
Lendian
Table 8-5
I²C Passive Mode Device Configuration Field Descriptions
Bit Field
16-15 Slave Addr
Description
I²C Slave boot bus address
0 = I²C slave boot bus address is 0x00
1 = I²C slave boot bus address is 0x10 (default)
2 = I²C slave boot bus address is 0x20
3 = I²C slave boot bus address is 0x30
14
Boot Devices
13-12 Port
Boot Device[14] used in conjunction with Boot Devices [Use din conjunction with bits 3-1]
0 = Other boot modes
1= I²C Slave boot mode
I²C port number
0 = I²C0
1 = I²C1
2 = I²C2
3 = Reserved
11-9 ARM PLL Setting The PLL default settings are determined by the [11:9] bits. This will set the PLL to the maximum clock setting for the device.
Table 8-27 shows settings for various input clock frequencies.
8
Boot Master
Boot Master select
0 = ARM is boot master
1 = C66x is boot master
7-5 SYS PLL Setting The PLL default settings are determined by the [7:5] bits. This will set the PLL to the maximum clock setting for the device.
Table 8-27 shows settings for various input clock frequencies.
4
Min
Minimum boot configuration select bit.
0 = Minimum boot pin select disabled
1 = Minimum boot pin select enabled.
When Min = 1, a predetermined set of values is configured (see the Device Configuration Field Descriptions table for
configuration bits with a "(default)" tag added in the description column).
When Min = 0, all fields must be independently configured.
3-1 Boot Devices Boot Devices[3:1] used in conjunction with Boot Device [14]
000 = I²C Slave
Others = Other boot modes
0
Lendian
End of Table 8-5
Endianess
0 = Big endian
1 = Little endian
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Device Boot and Configuration 213