TCI6636K2H Datasheet, PDF (12/362 Pages) Texas Instruments – Multicore DSP+ARM KeyStone II System-on-Chip (SoC)

TCI6636K2H
SPRS835F—February 2012—Revised October 2013
Table 8-14
Table 8-15
Table 8-16
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Table 8-18
Table 8-19
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Table 8-21
Table 8-22
Table 8-23
Table 8-24
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Table 8-27
Table 8-28
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Table 8-36
Table 8-37
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Table 8-41
Table 8-42
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Table 8-47
Table 8-48
Table 8-49
Table 8-50
Table 8-51
Table 8-52
Table 8-53
Table 8-54
Table 8-55
Table 8-56
HyperLink Boot Device Configuration Field
Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221
UART Boot Configuration Field Descriptions 222
Boot Parameter Table Common Parameters 223
EMIF16 Boot Parameter Table. . . . . . . . . . . . . . 223
SRIO Boot Parameter Table . . . . . . . . . . . . . . . . 224
Ethernet Boot Parameter Table . . . . . . . . . . . . 225
PCIe Boot Parameter Table. . . . . . . . . . . . . . . . . 226
I²C Boot Parameter Table . . . . . . . . . . . . . . . . . . 227
SPI Boot Parameter Table . . . . . . . . . . . . . . . . . . 227
HyperLink Boot Parameter Table . . . . . . . . . . . 228
UART Boot Parameter Table . . . . . . . . . . . . . . . 228
NAND Boot Parameter Table . . . . . . . . . . . . . . . 229
DDR3 Boot Parameter Table . . . . . . . . . . . . . . . 230
System PLL Configuration . . . . . . . . . . . . . . . . . 231
ARM PLL Configuration . . . . . . . . . . . . . . . . . . . . 232
Device Configuration Pins . . . . . . . . . . . . . . . . . 233
Device State Control Registers . . . . . . . . . . . . . 234
Device Status Register Field Descriptions. . . 238
Device Configuration Register Field
Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239
JTAG ID Register Field Descriptions . . . . . . . . 239
LRESETNMI PIN Status Register Field
Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240
LRESETNMI PIN Status Clear Register Field
Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241
Reset Status Register Field Descriptions . . . . 242
Reset Status Clear Register Field
Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243
Boot Complete Register Field Descriptions . 244
Power State Control Register Field
Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245
NMI Generation Register Field Descriptions 246
IPC Generation Registers Field Descriptions 247
IPC Acknowledgement Registers Field
Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247
IPC Generation Registers Field Descriptions 248
IPC Acknowledgement Register Field
Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248
Timer Input Selection Field Description . . . . 249
Timer Output Selection Field Description. . . 252
Reset Mux Register Field Descriptions . . . . . . 253
Device Speed Register Field Descriptions. . . 254
ARM Endian Configuration Register 0 Field
Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255
ARM Endian Configuration Register 1 Field
Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255
ARM Endian Configuration Register 2 Field
Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 256
Chip Miscellaneous Control Register
(CHIP_MISC_CTL0) Field Descriptions . . . . . . 256
Chip Miscellaneous Control Register
(CHIP_MISC_CTL1) Field Descriptions . . . . . . 257
System Endian Status Register Descriptions 258
SYNECLK_PINCTL Register Descriptions . . . . 258
USB_PHY_CTL0 Register Field Descriptions. 259
Table 8-57
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Table 8-59
Table 8-60
Table 8-61
Table 9-1
Table 9-2
Table 9-3
Table 9-4
Table 10-1
Table 10-2
Table 10-3
Table 10-4
Table 10-5
Table 10-6
Table 10-7
Table 10-8
Table 10-9
Table 10-10
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Table 10-14
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Table 10-24
Table 10-25
Table 10-26
Table 10-27
Table 10-28
Table 10-29
Table 10-30
Table 10-31
USB_PHY_CTL1 Register Field Descriptions .260
USB_PHY_CTL2 Register Field Descriptions .261
USB_PHY_CTL3 Register Field Descriptions .262
USB_PHY_CTL4 Register Field Descriptions .263
USB_PHY_CTL5 Register Field Descriptions .265
Absolute Maximum Ratings . . . . . . . . . . . . . . . .266
Recommended Operating Conditions . . . . . .267
Electrical Characteristics. . . . . . . . . . . . . . . . . . . .268
Power Supply to Peripheral I/O Mapping . . .269
Power Supply Rails on the TCI6636K2H . . . . .270
Core Before IO Power Sequencing . . . . . . . . . .272
IO-Before-Core Power Sequencing. . . . . . . . . .275
Clock Sequencing . . . . . . . . . . . . . . . . . . . . . . . . . .277
SmartReflex 4-Pin 6-bit VID Interface Switching
Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . .278
Power Domains . . . . . . . . . . . . . . . . . . . . . . . . . . . .280
Clock Domains . . . . . . . . . . . . . . . . . . . . . . . . . . . . .281
PSC Register Memory Map . . . . . . . . . . . . . . . . .282
Reset Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .287
Reset Timing Requirements . . . . . . . . . . . . . . . .290
Reset Switching Characteristics . . . . . . . . . . . . .291
Boot Configuration Timing Requirements . .291
Main PLL Controller Module Clock Domains
Internal and Shared Local Clock Dividers . . . .295
Main PLL Stabilization, Lock, and Reset
Times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .296
PLL Controller Registers (Including Reset
Controller) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .297
PLL Secondary Control Register Field
Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .298
PLL Controller Divider Register Field
Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .298
PLL Controller Clock Align Control Register Field
Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .299
PLLDIV Divider Ratio Change Status Register
Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . .300
SYSCLK Status Register Field Descriptions. . .300
Reset Type Status Register Field
Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .301
Reset Control Register Field Descriptions . . .301
Reset Configuration Register Field
Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .302
Reset Isolation Register Field Descriptions . .303
Main PLL Control Register 0 (MAINPLLCTL0)
Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . .303
Main PLL Control Register 1 (MAINPLLCTL1)
Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . .304
ARM PLL Control Register 0 Field
Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .305
ARM PLL Control Register 1Field
Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .305
Main PLL Controller/ARM/SRIO/HyperLink/PCIe/
USB Clock Input Timing Requirements . . . . . .305
DDR3A PLL and DDR3B PLL Control Register 0
Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . .310
DDR3A PLL and DDR3B PLL Control Register 1
Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . .310
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and
other important disclaimers. PRODUCTION DATA.