TCI6636K2H Datasheet, PDF (8/362 Pages) Texas Instruments – Multicore DSP+ARM KeyStone II System-on-Chip (SoC)

TCI6636K2H
SPRS835F—February 2012—Revised October 2013
10.6 DDR3A PLL and DDR3B PLL . . . . . . . . . . . . . . . . . . . . . . . 309
10.6.1 DDR3A PLL and DDR3B PLL Control Registers 309
10.6.2 DDR3A PLL and DDR3B PLL Device-Specific
Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 311
10.6.3 DDR3 PLL Input Clock Electrical Data/Timing 311
10.7 PASS PLL. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 311
10.7.1 PASS PLL Local Clock Dividers . . . . . . . . . . . . . . . 312
10.7.2 PASS PLL Control Registers. . . . . . . . . . . . . . . . . . 312
10.7.3 PASS PLL Device-Specific Information . . . . . . . 313
10.7.4 PASS PLL Input Clock Electrical Data/Timing . 314
10.8 External Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 314
10.8.1 External Interrupts Electrical Data/Timing . . . 314
10.9 DDR3A and DDR3B Memory Controllers. . . . . . . . . . . 316
10.9.1 DDR3 Memory Controller Device-Specific
Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 316
10.9.2 DDR3 Slew Rate Control . . . . . . . . . . . . . . . . . . . . 317
10.9.3 DDR3 Memory Controller Electrical
Data/Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 317
10.10 I²C Peripheral . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 317
10.10.1 I²C Device-Specific Information . . . . . . . . . . . . 317
10.10.2 I²C Peripheral Register Description . . . . . . . . . 318
10.10.3 I²C Electrical Data/Timing. . . . . . . . . . . . . . . . . . 319
10.11 SPI Peripheral . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 321
10.11.1 SPI Electrical Data/Timing. . . . . . . . . . . . . . . . . . 321
10.12 HyperLink Peripheral. . . . . . . . . . . . . . . . . . . . . . . . . . . . 324
10.13 UART Peripheral . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 326
10.14 PCIe Peripheral . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 327
10.15 Packet Accelerator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 327
10.16 Security Accelerator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 328
10.17 Network Coprocessor Gigabit Ethernet (GbE) Switch
Subsystem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 328
10.18 SGMII Management Data Input/Output (MDIO) . . 330
10.19 Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 331
10.19.1 Timers Device-Specific Information . . . . . . . . 331
10.19.2 Timers Electrical Timing . . . . . . . . . . . . . . . . . . . 331
10.20 Rake Search Accelerator (RSA). . . . . . . . . . . . . . . . . . . .332
10.21 Enhanced Viterbi-Decoder Coprocessor (VCP2) . . .332
10.22 Turbo Decoder Coprocessor (TCP3d) . . . . . . . . . . . . .332
10.23 Turbo Encoder Coprocessor (TCP3e). . . . . . . . . . . . . .332
10.24 Bit Rate Coprocessor (BCP) . . . . . . . . . . . . . . . . . . . . . . .332
10.25 Serial RapidIO (SRIO) Port . . . . . . . . . . . . . . . . . . . . . . . .333
10.25.1 Serial RapidIO Device-Specific Information . .333
10.26 General-Purpose Input/Output (GPIO) . . . . . . . . . . . .333
10.26.1 GPIO Device-Specific Information. . . . . . . . . . .333
10.26.2 GPIO Peripheral Register Description . . . . . . .333
10.26.3 GPIO Electrical Data/Timing . . . . . . . . . . . . . . . .334
10.27 Semaphore2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .334
10.28 Antenna Interface Subsystem 2 (AIF2) . . . . . . . . . . . .335
10.29 Receive Accelerator Coprocessor (RAC) . . . . . . . . . . .337
10.30 Transmit Accelerator Coprocessor (TAC) . . . . . . . . . .337
10.31 Fast Fourier Transform Coprocessor (FFTC) . . . . . . .337
10.32 Universal Serial Bus 3.0 (USB 3.0) . . . . . . . . . . . . . . . . .338
10.33 Universal Subscriber Identity Module (USIM). . . . . .338
10.34 EMIF16 Peripheral . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .338
10.34.1 EMIF16 Electrical Data/Timing . . . . . . . . . . . . . .338
10.35 Emulation Features and Capability . . . . . . . . . . . . . . .342
10.35.1 Chip Level Features . . . . . . . . . . . . . . . . . . . . . . . .343
10.35.2 ICEPick Module . . . . . . . . . . . . . . . . . . . . . . . . . . . .344
10.36 Debug Port (EMUx) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .346
10.36.1 Concurrent Use of Debug Port . . . . . . . . . . . . . .347
10.36.2 Master ID for HW and SW Messages. . . . . . . . .348
10.36.3 SoC Cross-Triggering Connection. . . . . . . . . . .349
10.36.4 Peripherals-Related Debug Requirement. . . .349
10.36.5 Advance Event Triggering (AET) . . . . . . . . . . . .351
10.36.6 Trace . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .352
10.36.7 IEEE 1149.1 JTAG . . . . . . . . . . . . . . . . . . . . . . . . . . .352
11 Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .354
12 Mechanical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .357
12.1 Thermal Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .357
12.2 Packaging Information . . . . . . . . . . . . . . . . . . . . . . . . . . . .357
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and
other important disclaimers. PRODUCTION DATA.