TCI6636K2H Datasheet, PDF (308/362 Pages) Texas Instruments – Multicore DSP+ARM KeyStone II System-on-Chip (SoC)

TCI6636K2H
Multicore DSP+ARM KeyStone II System-on-Chip (SoC)
SPRS835F—October 2013
3 If AIF2 is used then the Max allowed jitter on SYSCLK(N|P) is 4ps RMS
Figure 10-21 Main PLL Controller/SRIO/HyperLink/PCIe/USB Clock Input Timing
<CLK_NAME>CLKN
1
2
3
<CLK_NAME>CLKP
4
5
Figure 10-22 Main PLL Transition Time
peak-to-peak Differential Input
Voltage (250 mV to 2 V)
0
200 mV Transition Voltage Range
T_R = 50 ps Min to 350 ps Max
for the 200-mV Transition Voltage Range
Figure 10-23 HYP0CLK, HYP1CLK, and PCIECLK Rise and Fall Times
T_C Reference Clock Period
peak-to-peak
Differential
Input Voltage
0
(400 mV to 1100 mV)
Max T_R = 0.2 _× T_C from
10% to 90% of the
peak-to-peak
Differential Voltage
10% to 90%
of peak-to-peak
Voltage
Max T_F = 0.2 _× T_C from
90% to 10% of the
peak-to-peak
Differential Voltage
308 TCI6636K2H Peripheral Information and Electrical Specifications
Copyright 2013 Texas Instruments Incorporated
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