TCI6636K2H Datasheet, PDF (310/362 Pages) Texas Instruments – Multicore DSP+ARM KeyStone II System-on-Chip (SoC)

TCI6636K2H
Multicore DSP+ARM KeyStone II System-on-Chip (SoC)
SPRS835F—October 2013
Register’’ on page 240 for the address location of the registers and locking and unlocking sequences for accessing the
registers. These registers are reset on POR only.
.
Figure 10-26 DDR3A PLL and DDR3B PLL Control Register 0 (DDR3APLLCTL0/DDR3BPLLCTL0)
31
24
23
22
19
18
6
5
0
BWADJ[7:0]
BYPASS
CLKOD
PLLM
PLLD
RW-0000 1001
RW-1
RW-0001
RW-0000000010011
RW-000000
Legend: RW = Read/Write; -n = value after reset
Table 10-30 DDR3A PLL and DDR3B PLL Control Register 0 Field Descriptions
Bit
Field
Description
31-24 BWADJ[7:0]
BWADJ[11:8] and BWADJ[7:0] are located in DDR3PLLCTL0 and DDR3PLLCTL1 registers. BWADJ[11:0] should be
programmed to a value equal to half of PLLM[12:0] value (round down if PLLM has an odd value) Example: If PLLM = 15,
then BWADJ = 7
23
BYPASS
PLL bypass mode:
0 = PLL is not in BYPASS mode
1 = PLL is in BYPASS mode
22-19 CLKOD
A 4-bit field that selects the values for the PLL post divider. Valid post divider values are 1 and even values from 2 to 16.
CLKOD field is loaded with output divide value minus 1
18-6 PLLM
A 13-bit field that selects the values for the PLL multiplication factor. PLLM field is loaded with the multiply factor minus
1
5-0 PLLD
End of Table 10-30
A 6-bit field that selects the values for the reference (input) divider. PLLD field is loaded with reference divide value
minus 1
Figure 10-27 DDR3A PLL and DDR3B PLL Control Register 1 (DDR3APLLCTL0/DDR3BPLLCTL1)
31
15
14
13
7
6
5
4
Reserved
PLLRST
Reserved
ENSAT
Reserved
RW - 00000000000000000
RW-0
RW-0000000
RW-0
R-00
Legend: RW = Read/Write; -n = value after reset
3
0
BWADJ[11:8]
RW- 0000
Table 10-31 DDR3A PLL and DDR3B PLL Control Register 1 Field Descriptions
Bit
Field
Description
31-15 Reserved
Reserved
14
PLLRST
PLL Reset bit
0 = PLL Reset is released
1 = PLL Reset is asserted
13-7 Reserved
Reserved
6
ENSAT
Needs to be set to 1 for proper PLL operation
5-4 Reserved
Reserved
3-0 BWADJ[11:8]
End of Table 10-31
BWADJ[11:8] and BWADJ[7:0] are located in DDRPLLCTL0 and DDRPLLCTL1 registers. BWADJ[11:0] should be
programmed to a value equal to half of PLLM[12:0] value (round down if PLLM has an odd value) Example: If PLLM = 15,
then BWADJ = 7
310 TCI6636K2H Peripheral Information and Electrical Specifications
Copyright 2013 Texas Instruments Incorporated
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