TCI6636K2H Datasheet, PDF (330/362 Pages) Texas Instruments – Multicore DSP+ARM KeyStone II System-on-Chip (SoC)

TCI6636K2H
Multicore DSP+ARM KeyStone II System-on-Chip (SoC)
SPRS835F—October 2013
10.18 SGMII Management Data Input/Output (MDIO)
The management data input/output (MDIO) module implements the 802.3 serial management interface to
interrogate and control up to 32 Ethernet PHY(s) connected to the device, using a shared two-wire bus. Application
software uses the MDIO module to configure the auto-negotiation parameters of each PHY attached to the EMAC,
retrieve the negotiation results, and configure required parameters in the gigabit Ethernet (GbE) switch subsystem
for correct operation. The module allows almost transparent operation of the MDIO interface, with very little
attention from the C66x CorePac. For more information, see the Gigabit Ethernet (GbE) Switch Subsystem for
KeyStone Devices User Guide in 2.4 ‘‘Related Documentation from Texas Instruments’’ on page 19.
Table 10-50 MDIO Timing Requirements
(see Figure 10-49)
No.
1 tc(MDCLK)
Cycle time, MDCLK
2 tw(MDCLKH)
Pulse duration, MDCLK high
3 tw(MDCLKL)
Pulse duration, MDCLK low
4 tsu(MDIO-MDCLKH) Setup time, MDIO data input valid before MDCLK high
5 th(MDCLKH-MDIO) Hold time, MDIO data input valid after MDCLK high
tt(MDCLK)
End of Table 10-50
Transition time, MDCLK
Min
Max
Unit
400
ns
180
ns
180
ns
100
ns
0
ns
5
ns
Figure 10-49 MDIO Input Timing
MDCLK
MDIO
(Input)
1
2
3
4
5
Table 10-51 MDIO Switching Characteristics
(see Figure 10-50)
No.
Parameter
6
td(MDCLKH-MDIO) Delay time, MDCLK high to MDIO data output valid
7
th(MDCLKH-MDIO) Hold time, MDIO data output valid after MDCLK high
8
td(MDCLKH-MDIO)
End of Table 10-51
Delay time, MDCLK high to MDIO Hi-Z
Figure 10-50 MDIO Output Timing
1
MDCLK
MDIO
(Ouput)
7
6
Min
Max
Unit
10
300
ns
10
ns
10
300
ns
7
8
330 TCI6636K2H Peripheral Information and Electrical Specifications
Copyright 2013 Texas Instruments Incorporated
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