TCI6636K2H Datasheet, PDF (336/362 Pages) Texas Instruments – Multicore DSP+ARM KeyStone II System-on-Chip (SoC)

TCI6636K2H
Multicore DSP+ARM KeyStone II System-on-Chip (SoC)
SPRS835F—October 2013
Table 10-57 AIF2 Timer Module Timing Requirements (Part 2 of 2)
See Figure 10-51, Figure 10-54, Figure 10-55, and Figure 10-56
No.
8 tsu(RP1FBN-RP1CLKP) Setup time - RP1FBN valid before RP1CLKP high
8 tsu(RP1FBN-RP1CLKN) Setup time - RP1FBN valid before RP1CLKN low
8 tsu(RP1FBN-RP1CLKP) Setup time - RP1FBP valid before RP1CLKP high
8 tsu(RP1FBN-RP1CLKN) Setup time - RP1FBP valid before RP1CLKN low
9 th(RP1FBN-RP1CLKP)
Hold time - RP1FBN valid after RP1CLKP high
9 th(RP1FBN-RP1CLKN)
Hold time - RP1FBN valid after RP1CLKN low
9 th(RP1FBN-RP1CLKP)
Hold time - RP1FBP valid after RP1CLKP high
9 th(RP1FBN-RP1CLKN)
Hold time - RP1FBP valid after RP1CLKN low
PHY Sync and Radio Sync Pulses
10 tw(PHYSYNCH)
Pulse duration, PHYSYNC high
11 tc(PHYSYNC)
Cycle time, PHYSYNC pulse to PHYSYNC pulse
12 tw(RADSYNCH)
Pulse duration, RADSYNC high
13 tc(RADSYNC)
End of Table 10-57
Cycle time, RADSYNC pulse to RADSYNC pulse
1 C1 = tc(RP1CLKN/P)
Figure 10-53 AIF2 RP1 Frame Synchronization Clock Timing
RP1CLKN
1
2
RP1CLKP
4
Figure 10-54 AIF2 RP1 Frame Synchronization Burst Timing
6
RP1CLKN
RP1CLKP
Min
Max
Unit
2
ns
2
ns
2
ns
2
ns
2
ns
2
ns
2
ns
2
ns
6.50
ns
10.00
ms
6.50
ns
1.00
ms
3
5
RP1FBP/N
7
RP1 Frame Burst BIT 0
8
RP1 Frame Burst BIT 2
9
Figure 10-55 AIF2 Physical Layer Synchronization Pulse Timing
11
10
PHYSYNC
RP1 Frame Burst BIT N
Figure 10-56 AIF2 Radio Synchronization Pulse Timing
13
12
RADSYNC
336 TCI6636K2H Peripheral Information and Electrical Specifications
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