TCI6636K2H Datasheet, PDF (196/362 Pages) Texas Instruments – Multicore DSP+ARM KeyStone II System-on-Chip (SoC)

TCI6636K2H
Multicore DSP+ARM KeyStone II System-on-Chip (SoC)
SPRS835F—October 2013
7.3 Switch Fabric Connections Matrix - Configuration Space
The figures below show the connections between masters and slaves through various sections of the TeraNet.
Figure 7-5 TeraNet 3P_A
Bridge_12
Bridge_13
From TeraNet_3_A
Bridge_14
From TeraNet_3_C
CorePac_0 _M
CorePac_1 _M
CorePac_2 _M
CorePac_3 _M
CorePac_4 _M
CorePac_5 _M
CorePac_6 _M
CorePac_7 _M
Tracer_BCR_CFG
Tracer_QM_CFG1
MPU_3
MPU_2
Tracer_QM_CFG2
Tracer_SM
MPU_6
MPU_10
MPU_4
Tracer_
RAC_CFG_1
TNet_3P_H
CPU/3
S ^{MPU (´ 15)}
S ^{BCR CFG}
M
QM_SS_
CFG1
M
QM_SS_
CFG2
S ^Semaphore
S ^RAC_0_CFG
S ^RAC_1_CFG
Tracer
_EDMA
CC0 & CC4
TNet_3P_M
CPU/3
S
CC0
S ^{TC (´ 2)}
S
CC4
S ^{TC (´ 2)}
Tracer
_EDMA
CC1 - CC3
TNet_3P_C
CPU/3
S
CC1
S ^{TC (´ 4)}
S
CC2
S ^{TC (´ 4)}
S
CC3
S ^{TC (´ 2)}
MPU_9
Tracer_INTC
TNet_3P_L
CPU/3
S ^{ARM INTC}
S ^CP_INTC0-2
TETB
CorePac (´ 8)
DBG_TBR_SYS
(Debug_SS)
TBR_SYS_
ARM_CorePac
MPU_0
To TeraNet_3P_B
Tracer_CFG
To TeraNet_3P_Tracer
6636
196 System Interconnect
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