TCI6636K2H Datasheet, PDF (209/362 Pages) Texas Instruments – Multicore DSP+ARM KeyStone II System-on-Chip (SoC)

TCI6636K2H
Multicore DSP+ARM KeyStone II System-on-Chip (SoC)
SPRS835F—October 2013
Table 8-2
ARM Boot RAM Memory Map (Part 2 of 2)
Start Address
0xc5b_8200
0xc5b_8300
0x5b_8400
0xc5b_8500
0xc5b_8600
0xc5b_9fe0
0xc5b_c000
0xc5b_c180
0xc5b_c200
0xc5b_c300
0x5b_c400
0xc5b_c500
0xc5b_c600
0xc5b_dfe0
0xc5c_0000
End of Table 8-2
Size
0x100
0x100
0x100
0x100
0x19e0
0x1010
0x180
0x80
0x100
0x100
0x100
0x100
0x19e0
0x1010
0x4_0000
Boot stats, core 2
Boot log, core 2
Boot RAM call table, core 2
Boot parameter tables, core 2
Boot Data, core 2
Boot Trace, core 2
Boot Version string, core 3
Boot status stack, core 3
Boot stats, core 3
Boot log, core 3
Boot RAM call table, core 3
Boot parameter tables, core 3
Boot Data, core 3
Boot Trace, core 3
Secure MSMC
Description
8.1.2 Boot Modes Supported
The device supports several boot processes, which leverage the internal boot ROM. Most boot processes are
software-driven, using the BOOTMODE[15:0] device configuration inputs to determine the software configuration
that must be completed. From a hardware perspective, there are four possible boot modes:
• Public ROM Boot when the C6xx CorePac0 is the boot master — The C66x CorePac is released from reset
and begins executing from the L3 ROM base address. The ARM CorePac is also released from reset at the same
time as the C66xCorePac. Both the C66x CorePac and the ARM CorePac read the bootmode register inside
the bootCFG module to determine which is the boot master.
After the Boot ROM for the Cortex-A15 processor reads the bootmode to determine that the C66x CorePac is
the boot master, all Cortex-A15 processors stay idle by executing WFI instruction and waiting for the C66x
CorePac’s interrupt. The chip Boot ROM reads the bootmode register to determine that the C66x CorePac0 is
the boot master, then the C66x CorePac0 performs the boot process and the other C66x CorePacs execute an
IDLE instruction. After the boot process is completed, the C66x CorePac0 begins to execute the code
downloaded during the boot process. If the downloaded code included code for the other C66x cores and/or
the Cortex-A15 processor cores, the downloaded code may contain logic to write the code execution addresses
to the boot address register for the core that is to execute it. The C66x CorePac0 can then generate an interrupt
to the core causing it to execute the code. When they receive the IPC interrupt, the rest of the C66x CorePacs
and the ARM CorePac complete boot management operations and begin executing from the predefined
location in memory.
• Public ROM Boot when the ARM CorePac Core0 is the boot master — The only difference between this boot
mode and and when the C66x CorePac is the boot master, is that the ARM CorePac performs the boot process
while the C66x CorePacs execute idle instructions. When the ARM CorePac Core0 finishes the boot process,
it may send interrupts to the C66x CorePacs and Cortex-A15 processor cores through IPC registers. The C66x
CorePacs complete the boot management operations and begin executing from the predefined locations.
• Secure ROM Boot when the C66x CorePac0 is the boot master —The C66x CorePac0 and the ARM CorePac
Core0 are released from reset simultaneously and the C66x CorePac0 begins executing from secure ROM. The
C66x CorePac0 performs the boot process includingany authentication and decryption required on the
bootloaded image for the C66x CorePacs and for the ARM CorePac prior to beginning execution.
Copyright 2013 Texas Instruments Incorporated
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Device Boot and Configuration 209