TCI6636K2H Datasheet, PDF (264/362 Pages) Texas Instruments – Multicore DSP+ARM KeyStone II System-on-Chip (SoC)

TCI6636K2H
Multicore DSP+ARM KeyStone II System-on-Chip (SoC)
SPRS835F—October 2013
Table 8-60 USB_PHY_CTL4 Register Field Descriptions (Part 2 of 2)
Bit
Field
Description
20-19 PHY_REFCLKSEL
Reference Clock Select for PLL Block.
Selects reference clock source for the HS PLL block.
11 = HS PLL uses EXTREFCLK as reference.
10 = HS PLL uses either ref_pad_clk_{p,m} or ref_alt_clk_{p,m} as reference.
x0 = Reserved.
18
PHY_COMMONONN
Common Block Power-Down Control.
Controls the power-down signals in the HS Bias and PLL blocks when the USB3.0 PHY is in Suspend or
Sleep mode.
1 = In Suspend or Sleep mode, the HS Bias and PLL blocks are powered down.
0 = In Suspend or Sleep mode, the HS Bias and PLL blocks remain powered and continue to draw
current.
17
Reserved
Reserved
16
PHY_OTG_VBUSVLDEXTSEL
External VBUS Valid Select.
Selects the VBUSVLDEXT input or the internal Session Valid comparator to indicate when the VBUS
signal on the USB cable is valid.
1 = VBUSVLDEXT input is used.
0 = Internal Session Valid comparator is used.
15
PHY_OTG_OTGDISABLE
OTG Block Disable.
Powers down the OTG block, which disables the VBUS Valid and Session End comparators. The Session
Valid comparator (the output of which is used to enable the pull-up resistor on DP in Device mode) is
always on irrespective of the state of otgdisable. If the application does not use the OTG function,
setting this signal to high to save power.
1 = OTG block is powered down.
0 = OTG block is powered up.
14-12 PHY_PC_TX_VBOOST_LVL
Tx Voltage Boost Level.
Sets the boosted transmit launch amplitude (mV_ppd).
The default setting is intended to set the launch amplitude to approximately 1,008mV_ppd.
+1 = results in a +156 mV_ppd change in the Tx launch amplitude.
-1 = results in a -156 mV_ppd change in the Tx launch amplitude.
11-7 PHY_PC_LANE0_TX_TERM_OFFSET Transmitter Termination Offset.
Enables adjusting the transmitter termination value from the default value of 60 Ω.
6-0
Reserved
Reserved
End of Table 8-60
Figure 8-43
31
USB_PHY_CTL5 Register
21
Reserved
R-0
20
PHY_REF_CLKDIV2
R/W-0
19
13
PHY_MPLL_MULTIPLIER[6:0]
R/W +0011001
12
4
PHY_SSC_REF_CLK_SEL
R/W-000000000
Legend: R = Read only; R/W = Read/Write, -n = value after reset
3
Reserved
R-0
2
0
PHY_SSC_RANGE
R/W-000
264 Device Boot and Configuration
Copyright 2013 Texas Instruments Incorporated
Submit Documentation Feedback