TCI6636K2H Datasheet, PDF (242/362 Pages) Texas Instruments – Multicore DSP+ARM KeyStone II System-on-Chip (SoC)

TCI6636K2H
Multicore DSP+ARM KeyStone II System-on-Chip (SoC)
SPRS835F—October 2013
The Reset Status Register is shown in the figure and table below.
Figure 8-18 Reset Status Register (RESET_STAT)
31 30
87
6
5
4
3
2
1
0
GR
Reserved
LR7
LR6
LR5
LR4
LR3
LR2
LR1
LR0
R-1
R- 000 0000 0000 0000 0000 0000
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
Legend: R = Read only; -n = value after reset
Table 8-36 Reset Status Register Field Descriptions
Bit
Field
31 GR
30-8 Reserved
7 LR7
6 LR6
5 LR5
4 LR4
3 LR3
2 LR2
1 LR1
0 LR0
End of Table 8-36
Description
Global reset status
0 = Device has not received a global reset.
1 = Device received a global reset.
Reserved.
C66x CorePac7 reset status
0 = C66x CorePac7 has not received a local reset.
1 = C66x CorePac7 received a local reset.
C66x CorePac6 reset status
0 = C66x CorePac6 has not received a local reset.
1 = C66x CorePac6 received a local reset.
C66x CorePac5 reset status
0 = C66x CorePac5 has not received a local reset.
1 = C66x CorePac5 received a local reset.
C66x CorePac4 reset status
0 = C66x CorePac4 has not received a local reset.
1 = C66x CorePac4received a local reset.
C66x CorePac3 reset status
0 = C66x CorePac3 has not received a local reset.
1 = C66x CorePac3 received a local reset.
C66x CorePac2 reset status
0 = C66x CorePac2 has not received a local reset.
1 = C66x CorePac2 received a local reset.
C66x CorePac1 reset status
0 = C66x CorePac1 has not received a local reset.
1 = C66x CorePac1 received a local reset.
C66x CorePac0 reset status
0 = C66x CorePac0 has not received a local reset.
1 = C66x CorePac0 received a local reset.
8.2.3.8 Reset Status Clear (RESET_STAT_CLR) Register
The RESET_STAT bits can be cleared by writing 1 to the corresponding bit in the RESET_STAT_CLR register. The
Reset Status Clear Register is shown in the figure and table below.
242 Device Boot and Configuration
Copyright 2013 Texas Instruments Incorporated
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