TCI6636K2H Datasheet, PDF (246/362 Pages) Texas Instruments – Multicore DSP+ARM KeyStone II System-on-Chip (SoC)

TCI6636K2H
Multicore DSP+ARM KeyStone II System-on-Chip (SoC)
SPRS835F—October 2013
8.2.3.11 NMI Event Generation to C66x CorePac (NMIGRx) Register
NMIGRx registers generate NMI events to the corresponding C66x CorePac. The TCI6636K2H has
eight NMIGRx registers (NMIGR0 through NMIGR7). The NMIGR0 register generates an NMI event to C66x
CorePac0, the NMIGR1 register generates an NMI event to C66x CorePac1, and so on. Writing a 1 to the NMIG
field generates an NMI pulse. Writing a 0 has no effect and Reads return 0 and have no other effect. The NMI event
generation to the C66x CorePac is shown in Figure 8-22 and described in Table 8-40.
Figure 8-22 NMI Generation Register (NMIGRx)
31
10
Reserved
NMIG
R-0000 0000 0000 0000 0000 0000 0000 000
RW-0
Legend: RW = Read/Write; -n = value after reset
Table 8-40 NMI Generation Register Field Descriptions
Bit Field
31-1 Reserved
0
NMIG
End of Table 8-40
Description
Reserved
Reads return 0
Writes:
0 = No effect
1 = Creates NMI pulse to the corresponding C66x CorePac — C66x CorePac0 for NMIGR0, etc.
8.2.3.12 IPC Generation (IPCGRx) Registers
The IPCGRx Registers facilitate inter-C66x CorePac interrupts.
The TCI6636K2H has twelve IPCGRx registers (IPCGR0 through IPCGR11 ). These registers can be used by
external hosts or CorePacs to generate interrupts to other CorePacs. A write of 1 to the IPCG field of the IPCGRx
register generates an interrupt pulse to the C66x CorePacx (0 <= x <= 7) or ARM CorePac core (x-8) (8<=x<=11).
These registers also provide a Source ID facility identifying up to 28 different sources of interrupts. Allocation of
source bits to source processor and meaning is entirely based on software convention. The register field descriptions
are given in the following tables. There can be numerous sources for these registers as this is completely controlled
by software. Any master that has access to BOOTCFG module space can write to these registers. The IPC Generation
Register is shown in Figure 8-23 and described in Table 8-41.
Figure 8-23 IPC Generation Registers (IPCGRx)
31
30
29
28 27
87
6
5
43
10
SRCS27 SRCS26 SRCS25 SRCS24
SRCS23 – SRCS4
SRCS3 SRCS2 SRCS1 SRCS0
Reserved
IPCG
RW +0 RW +0 RW +0 RW +0
RW +0 (per bit field)
RW +0 RW +0 RW +0 RW +0
R-000
RW +0
Legend: R = Read only; RW = Read/Write; -n = value after reset
246 Device Boot and Configuration
Copyright 2013 Texas Instruments Incorporated
Submit Documentation Feedback