TCI6636K2H Datasheet, PDF (259/362 Pages) Texas Instruments – Multicore DSP+ARM KeyStone II System-on-Chip (SoC)

Figure 8-38 USB_PHY_CTL0 Register
TCI6636K2H
Multicore DSP+ARM KeyStone II System-on-Chip (SoC)
SPRS835F—October 2013
10
9
8
7
6
5
PHY_RTUNE_REQ
Reserved
PHY_TC_VATESTENB PHY_TC_TEST_POWERDOWN_SSP PHY_TC_TEST_POWERDOWN_HSP
R/W-0
4
R-0
R/W-00
R/W-0
spacer
3
2
1
R/W-0
0
PHY_TC_LOOPBACKENB
Reserved
UTMI_VBAUSVLDEXT
UTMI_TXBITSTUFFENH
UTMI_TXBITSTUFFEN
R/W-0
R-0
R/W-0
R/W-0
R/W-0
Legend: R = Read only; W = Write only; -n = value after reset
Table 8-56 USB_PHY_CTL0 Register Field Descriptions (Part 1 of 2)
Bit
31-12
11
10
9
8-7
6
5
4
3
2
Field
Description
Reserved
Reserved
PHY_RTUNE_ACK
The PHY uses an external resistor to calibrate the termination impedances of the PHY's high-speed
inputs and outputs.
The resistor is shared between the USB2.0 high-speed outputs and the Super-speed I/O. Each time the
PHY is taken out of a reset, a termination calibration is performed. For SS link, the calibration can also be
requested externally by asserting the PHY_RTUNE_REQ. When the calibration is complete, the
PHY_RTUNE_ACK transitions low.
A resistor calibration on the SS link cannot be performed while the link is operational
PHY_RTUNE_REQ
See PHY_RTUNE_ACK.
Reserved
Reserved
PHY_TC_VATESTENB
Analog Test Pin Select.
Enables analog test voltages to be placed on the ID pin.
11 = Invalid setting.
10 = Invalid setting.
01 = Analog test voltages can be viewed or applied on ID.
00 = Analog test voltages cannot be viewed or applied on ID.
PHY_TC_TEST_POWERDOWN_SSP SS Function Circuits Power-Down Control.
Powers down all SS function circuitry in the PHY for IDDQ testing.
PHY_TC_TEST_POWERDOWN_HSP HS Function Circuits Power-Down Control
Powers down all HS function circuitry in the PHY for IDDQ testing.
PHY_TC_LOOPBACKENB
Loop-back Test Enable
Places the USB3.0 PHY in HS Loop-back mode, which concurrently enables the HS receive and transmit
logic.
1 = During HS data transmission, the HS receive logic is enabled.
0 = During HS data transmission, the HS receive logic is disabled.
Reserved
Reserved
UTMI_VBAUSVLDEXT
External VBUS Valid Indicator
Function: Valid in Device mode and only when the VBUSVLDEXTSEL signal is set to 1'b1. VBUSVLDEXT
indicates whether the VBUS signal on the USB cable is valid. In addition, VBUSVLDEXT enables the
pull-up resistor on the D+ line.
1 = VBUS signal is valid, and the pull-up resistor on D+ is enabled.
0 = VBUS signal is not valid, and the pull-up resistor on D+ is disabled.
Copyright 2013 Texas Instruments Incorporated
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