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| TCI6636K2H Datasheet, PDF (201/362 Pages) Texas Instruments – Multicore DSP+ARM KeyStone II System-on-Chip (SoC) | |||
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Table 7-3
TCI6636K2H
Multicore DSP+ARM KeyStone II System-on-Chip (SoC)
SPRS835FâOctober 2013
Configuration Space Interconnect - Section 1 (Part 2 of 2)
Slaves
Masters
EDMA2_TC1_WR - - - - - - - - - - - - - - - - - - - - - - - - - - -
EDMA2_TC2_RD 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12
EDMA2_TC2_WR 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12
EDMA2_TC3_RD - - - - - - - - - - - - - - - - - - - - - - - - - - -
EDMA2_TC3_WR - - - - - - - - - - - - - - - - - - - - - - - - - - -
EDMA3_CC_TR - - - - - - - - - - - - - - - - - - - - - - - - - - -
EDMA3_TC0_RD 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13
EDMA3_TC0_WR 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13
EDMA3_TC1_RD - - - - - - - - - - - - - - - - - - - - - - - - - - -
EDMA3_TC1_WR - - - - - - - - - - - - - - - - - - - - - - - - - - -
EDMA4_CC_TR - - - - - - - - - - - - - - - - - - - - - - - - - - -
EDMA4_TC0_RD - - - - - - - - - - - - - - - - - - - - - - - - - - -
EDMA4_TC0_WR - - - - - - - - - - - - - - - - - - - - - - - - - - -
EDMA4_TC1_RD - - - - - - - - - - - - - - - - - - - - - - - - - - -
EDMA4_TC1_WR - - - - - - - - - - - - - - - - - - - - - - - - - - -
FFTC_0
12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12
FFTC_1
12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12
FFTC_2
12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12
FFTC_3
12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12
HyperLink0_Master 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12
HyperLink1_Master 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12
MSMC_SYS
YYYYYYYYYYYYYYYYYYYYYYYYYYY
NETCP
---------------------------
PCIE
12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12
QM_Master1
---------------------------
QM_Master2
---------------------------
QM_SEC
- - - - 12 - - - - - - - - - - - - - - - - - - - - - -
RAC_(0-1)_BE0
---------------------------
RAC_(0-1)_BE1
---------------------------
SRIO
14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14
SRIO Packet DMA - - - - - - - - - - - - - - - - - - - - - - - - - - -
TAC_FEI_(0-2)
---------------------------
USB
---------------------------
End of Table 7-3
Copyright 2013 Texas Instruments Incorporated
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System Interconnect 201
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