TCI6636K2H Datasheet, PDF (267/362 Pages) Texas Instruments – Multicore DSP+ARM KeyStone II System-on-Chip (SoC)

TCI6636K2H
Multicore DSP+ARM KeyStone II System-on-Chip (SoC)
SPRS835F—October 2013
6 Level listed above is the passing level per EIA-JEDEC JESD22-C101E. JEDEC document JEP157 states that 250 V CDM allows safe manufacturing with a standard ESD control
process. Pins listed as 250 V may actually have higher performance.
7 Overshoot/Undershoot percentage relative to I/O operating values - for example the maximum overshoot value for 1.8 V LVCMOS signals is DVDD18 + 0.20 × DVDD18 and
maximum undershoot value would be V_SS - 0.20 × DVDD18
9.2 Recommended Operating Conditions
Table 9-2
Recommended Operating Conditions ^{(1) (2)}
CVDD
SR DSP core supply
CVDD1
DSP Core supply
CVDDT1
Cortex-A15 processor Core
supply
DVDD18
1.8-V supply I/O voltage
DVDD15
1.5-V supply I/O voltage
DDR3VREFSSTL DDR3A, DDR3B reference voltage
VDDAHV
AVDDx ⁽⁵⁾
SerDes regulator supply
PLL analog, DDR DLL supply
VDDALH
SerDes termination supply
DVDD33
USB
Initial ⁽³⁾
1000MHz -
Device
1200MHz -
Device
Min
0.95
SRVnom*0.95 ⁽⁴⁾
SRVnom*0.95 ⁽⁴⁾
Nom
1.0
SRVnom
SRVnom
0.902
0.95
0.902
0.95
1.71
1.425
0.49 × DVDD15
1.71
1.71
0.807
3.135
1.8
1.5
0.5 × DVDD15
1.8
1.8
0.85
3.3
Max Unit
1.05 V
SRVnom*1.05 _V
SRVnom*1.05 _V
0.997 V
0.997 V
1.89 V
1.575 V
0.51 × DVDD15 V
1.89 V
1.89 V
0.892 V
3.465 V
VDDUSB
USB
0.807
0.85
0.892 V
V_SS
Ground
V_IH ⁽⁶⁾
High-level input voltage
LVCMOS (1.8 V)
I²C
DDR3A, DDR3B EMIF
V_IL ⁽⁶⁾
Low-level input voltage
LVCMOS (1.8 V)
DDR3A, DDR3B EMIF
I²C
Commercial
T_C
Operating case temperature
Extended
End of Table 9-2
0
0.65 × DVDD18
0.7 × DVDD18
VREFSSTL + 0.1
-0.3
0
-40
0
0V
V
V
V
0.35 × DVDD18 V
VREFSSTL - 0.1 V
0.3 × DVDD18 V
100 °C
100 °C
1 All differential clock inputs comply with the LVDS Electrical Specification, IEEE 1596.3-1996 and all SerDes I/Os comply with the XAUI Electrical Specification, IEEE 802.3ae-2002.
2 All SerDes I/Os comply with the XAUI Electrical Specification, IEEE 802.3ae-2002.
3 Users are required to program their board CVDD supply initial value to 1.0 V on the device. The initial CVDD voltage at power-on will be 1.0V nominal and it must
transition to VID set value, immediately after being presented on the VCNTL pins. This is required to maintain full power functionality and reliability targets guaranteed
by TI.
4 SRVnom refers to the unique SmartReflex core supply voltage that has a potential range of 0.8 V and 1.1 V which preset from the factory for each individual device. Your device
may never be programmed to operate at the upper range but has been designed accordingly should it be determined to be acceptable or necessary. Power supplies
intended to support the variable SRV function shall be capable of providing a 0.8V-1.1V dynamic range using a 4- or 6-bit binary input value which as provided by the DSP
SmartReflex output.
5 Where x=1,2,3,4... to indicate all supplies of the same kind.
6 For USB High-Speed, Full-Speed, and Low -Speed modes, USB I/Os adhere to Universal Serial Bus, revision 2.0 standard. For USB Super-Speed mode, USB I/Os adhere to
Universal Serial Bus, revision 3.1 specification, revision 1.0 standard.
Copyright 2013 Texas Instruments Incorporated
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Device Operating Conditions 267