TCI6636K2H Datasheet, PDF (299/362 Pages) Texas Instruments – Multicore DSP+ARM KeyStone II System-on-Chip (SoC)

TCI6636K2H
Multicore DSP+ARM KeyStone II System-on-Chip (SoC)
SPRS835F—October 2013
Table 10-17 PLL Controller Divider Register Field Descriptions (Part 2 of 2)
Bit
Field
Description
14-8 Reserved
7-0
RATIO
End of Table 10-17
Reserved. The reserved bit location is always read as 0. A value written to this field has no effect.
Divider ratio bits (See footnote of Figure 10-9)
0h = ÷1. Divide frequency by 1
1h = ÷2. Divide frequency by 2
2h = ÷3. Divide frequency by 3
3h = ÷4. Divide frequency by 4
4h - 4Fh = ÷5 to ÷80. Divide frequency range: divide frequency by 5 to divide frequency by 80.
10.5.2.3 PLL Controller Clock Align Control Register (ALNCTL)
The PLL Controller Clock Align Control Register (ALNCTL) is shown in Figure 10-10 and described in Table 10-18.
Figure 10-10 PLL Controller Clock Align Control Register (ALNCTL)
31
5
4
32
0
Reserved
ALN4 ALN3
Reserved
R-0
R/W-1 R/W-1
R-0
Legend: R/W = Read/Write; R = Read only; -n = value after reset, for reset value
Table 10-18 PLL Controller Clock Align Control Register Field Descriptions
Bit
Field
Description
31-5
Reserved
2-0
Reserved. This location is always read as 0. A value written to this field has no effect.
4
ALN4
3
ALN3
End of Table 10-18
SYSCLKn alignment. Do not change the default values of these fields.
0 = Do not align SYSCLKn to other SYSCLKs during GO operation. If SYSn in DCHANGE is set, SYSCLKn switches to the new
ratio immediately after the GOSET bit in PLLCMD is set.
1 = Align SYSCLKn to other SYSCLKs selected in ALNCTL when the GOSET bit in PLLCMD is set and SYSn in DCHANGE is 1.
The SYSCLKn rate is set to the ratio programmed in the RATIO bit in PLLDIVn.
10.5.2.4 PLLDIV Divider Ratio Change Status Register (DCHANGE)
Whenever a different ratio is written to the PLLDIVn registers, the PLL CTL flags the change in the DCHANGE
Status Register. During the GO operation, the PLL controller changes only the divide ratio of the SYSCLKs with the
bit set in DCHANGE. Note that the ALNCTL Register determines if that clock also needs to be aligned to other
clocks. The PLLDIV Divider Ratio Change Status Register is shown in Figure 10-11 and described in Table 10-19.
Figure 10-11 PLLDIV Divider Ratio Change Status Register (DCHANGE)
31
5
4
32
0
Reserved
SYS4 SYS3
Reserved
R-0
R/W-1 R/W-1
R-0
Legend: R/W = Read/Write; R = Read only; -n = value after reset, for reset value
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TCI6636K2H Peripheral Information and Electrical Specifications 299