TCI6636K2H Datasheet, PDF (273/362 Pages) Texas Instruments – Multicore DSP+ARM KeyStone II System-on-Chip (SoC)

TCI6636K2H
Multicore DSP+ARM KeyStone II System-on-Chip (SoC)
SPRS835F—October 2013
Table 10-2 Core Before IO Power Sequencing (Part 2 of 2)
Item
7
8
System State
• Device initialization requires 500 SYSCLK1 periods after the Power Stabilization Phase. The maximum clock period is 33.33 nsec, so a delay
of an additional 16 μs is required before a rising edge of POR. The clock must be active during the entire 16 μs.
• RESETFULL must be held low for at least 24 transitions of the SYSCLK1 after POR has stabilized at a high level.
9
• The rising edge of the RESETFULL will remove the reset to the eFuse farm allowing the scan to begin.
• Once device initialization and the eFuse farm scan are complete, the RESETSTAT signal is driven high. This delay will be 10000 to 50000
clock cycles.
End device initialization phase
10
• GPIO configuration bits must be valid for at least 12 transitions of the SYSCLK1 before the rising edge of RESETFULL.
11
• GPIO configuration bits must be held valid for at least 12 transitions of the SYSCLK1 after the rising edge of RESETFULL.
End of Table 10-2
Copyright 2013 Texas Instruments Incorporated
Submit Documentation Feedback
TCI6636K2H Peripheral Information and Electrical Specifications 273