TCI6636K2H Datasheet, PDF (243/362 Pages) Texas Instruments – Multicore DSP+ARM KeyStone II System-on-Chip (SoC)

TCI6636K2H
Multicore DSP+ARM KeyStone II System-on-Chip (SoC)
SPRS835F—October 2013
Figure 8-19 Reset Status Clear Register (RESET_STAT_CLR)
31 30
87
GR
Reserved
LR7
RW-0
R- 000 0000 0000 0000 0000 0000
RW-0
Legend: R = Read only; RW = Read/Write; -n = value after reset
6
LR6
RW-0
5
LR5
RW-0
4
LR4
RW-0
3
LR3
RW-0
2
LR2
RW-0
1
LR1
RW-0
0
LR0
RW-0
Table 8-37 Reset Status Clear Register Field Descriptions
Bit Field
31 GR
30-8 Reserved
7
LR7
6
LR6
5
LR5
4
LR4
3
LR3
2
LR2
1
LR1
0
LR0
End of Table 8-37
Description
Global reset clear bit
0 = Writing a 0 has no effect.
1 = Writing a 1 to the GR bit clears the corresponding bit in the RESET_STAT register.
Reserved.
C66x CorePac7 reset clear bit
0 = Writing a 0 has no effect.
1 = Writing a 1 to the LR7 bit clears the corresponding bit in the RESET_STAT register.
C66x CorePac6 reset clear bit
0 = Writing a 0 has no effect.
1 = Writing a 1 to the LR6 bit clears the corresponding bit in the RESET_STAT register.
C66x CorePac5 reset clear bit
0 = Writing a 0 has no effect.
1 = Writing a 1 to the LR5 bit clears the corresponding bit in the RESET_STAT register.
C66x CorePac4 reset clear bit
0 = Writing a 0 has no effect.
1 = Writing a 1 to the LR4 bit clears the corresponding bit in the RESET_STAT register.
C66x CorePac3 reset clear bit
0 = Writing a 0 has no effect.
1 = Writing a 1 to the LR3 bit clears the corresponding bit in the RESET_STAT register.
C66x CorePac2 reset clear bit
0 = Writing a 0 has no effect.
1 = Writing a 1 to the LR2 bit clears the corresponding bit in the RESET_STAT register.
C66x CorePac1 reset clear bit
0 = Writing a 0 has no effect.
1 = Writing a 1 to the LR1 bit clears the corresponding bit in the RESET_STAT register.
C66x CorePac0 reset clear bit
0 = Writing a 0 has no effect.
1 = Writing a 1 to the LR0 bit clears the corresponding bit in the RESET_STAT register.
8.2.3.9 Boot Complete (BOOTCOMPLETE) Register
The BOOTCOMPLETE register controls the BOOTCOMPLETE pin status to indicate the completion of the ROM
booting process. The Boot Complete Register is shown in the figure and table below.
Figure 8-20 Boot Complete Register (BOOTCOMPLETE)
31
12
11
10
9
8
7
6
5
4
3
2
1
0
Reserved
R,-0000 0000 0000
0000 0000
BC11
RW-0
BC10
RW-0
BC9
RW-0
BC8
RW-0
BC7
RW-0
BC6
RW-0
BC5
RW-0
BC4
RW-0
BC3
RW-0
BC
RW-0
BC1
RW-0
BC0
RW-0
Legend: R = Read only; RW = Read/Write; -n = value after reset
Copyright 2013 Texas Instruments Incorporated
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Device Boot and Configuration 243