TCI6636K2H Datasheet, PDF (10/362 Pages) Texas Instruments – Multicore DSP+ARM KeyStone II System-on-Chip (SoC)

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SYSCLK Status Register (SYSTAT) . . . . . . . . . . . 300
Reset Type Status Register (RSTYPE). . . . . . . . 300
Reset Control Register (RSTCTRL) . . . . . . . . . . 301
Reset Configuration Register (RSTCFG) . . . . . 302
Reset Isolation Register (RSISO) . . . . . . . . . . . . 302
Main PLL Control Register 0 (MAINPLLCTL0) 303
Main PLL Control Register 1 (MAINPLLCTL1) 304
ARM PLL Control Register 0 (ARMPLLCTL0) . 304
ARM PLL Control Register 1 (ARMPLLCTL1) . 305
Main PLL Controller/SRIO/HyperLink/PCIe/USB
Clock Input Timing . . . . . . . . . . . . . . . . . . . . . . . . 308
Main PLL Transition Time . . . . . . . . . . . . . . . . . . 308
HYP0CLK, HYP1CLK, and PCIECLK Rise and Fall
Times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 308
USBCLK Rise and Fall Times . . . . . . . . . . . . . . . . 309
DDR3A PLL and DDR3B PLL Block Diagram . 309
DDR3A PLL and DDR3B PLL Control Register 0
(DDR3APLLCTL0/DDR3BPLLCTL0) . . . . . . . . . . 310
DDR3A PLL and DDR3B PLL Control Register 1
(DDR3APLLCTL0/DDR3BPLLCTL1) . . . . . . . . . . 310
DDR3 PLL DDRCLK Timing . . . . . . . . . . . . . . . . . 311
PASS PLL Block Diagram . . . . . . . . . . . . . . . . . . . 312
PASS PLL Control Register 0 (PASSPLLCTL0) 312
PASS PLL Control Register 1 (PASSPLLCTL1) 313
PASS PLL Timing . . . . . . . . . . . . . . . . . . . . . . . . . . 314
NMI and LRESET Timing . . . . . . . . . . . . . . . . . . . 315
I²C Module Block Diagram . . . . . . . . . . . . . . . . . 318
I²C Receive Timings . . . . . . . . . . . . . . . . . . . . . . . 320
I²C Transmit Timings . . . . . . . . . . . . . . . . . . . . . . 321
SPI Master Mode Timing Diagrams — Base
Timings for 3-Pin Mode . . . . . . . . . . . . . . . . . . . . 323
SPI Additional Timings for 4-Pin Master Mode
with Chip Select Option . . . . . . . . . . . . . . . . . . . 323
HyperLink Station Management Clock
Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 325
TCI6636K2H
SPRS835F—February 2012—Revised October 2013
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HyperLink Station Management Transmit
Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .325
HyperLink Station Management Receive
Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .325
UART Receive Timing Waveform . . . . . . . . . . . .326
UART CTS (Clear-to-Send Input) — Autoflow
Timing Waveform . . . . . . . . . . . . . . . . . . . . . . . . . .326
UART Transmit Timing Waveform. . . . . . . . . . .327
UART RTS (Request-to-Send Output) – Autoflow
Timing Waveform . . . . . . . . . . . . . . . . . . . . . . . . . .327
MACID1 Register
(MMR Address 0x02620110) . . . . . . . . . . . . . . . .328
MACID2 Register
(MMR Address 0x02620114) . . . . . . . . . . . . . . . .328
RFTCLK Select Register (CPTS_RFTCLK_SEL) 329
MDIO Input Timing. . . . . . . . . . . . . . . . . . . . . . . . .330
MDIO Output Timing . . . . . . . . . . . . . . . . . . . . . . .330
Timer Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .331
GPIO Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .334
AIF2 RP1 Frame Synchronization Clock
Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .336
AIF2 RP1 Frame Synchronization Burst
Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .336
AIF2 Physical Layer Synchronization Pulse
Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .336
AIF2 Radio Synchronization Pulse Timing . . .336
AIF2 Timer External Frame Event Timing . . . .337
EMIF16 Asynchronous Memory Read Timing
Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .340
EMIF16 Asynchronous Memory Write Timing
Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .340
EMIF16 EM_WAIT Read Timing Diagram . . . .341
EMIF16 EM_WAIT Write Timing Diagram . . . .341
Trace Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .352
JTAG Test-Port Timing. . . . . . . . . . . . . . . . . . . . . .353
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and
other important disclaimers. PRODUCTION DATA.