TCI6636K2H Datasheet, PDF (2/362 Pages) Texas Instruments – Multicore DSP+ARM KeyStone II System-on-Chip (SoC)

TCI6636K2H
Multicore DSP+ARM KeyStone II System-on-Chip (SoC)
SPRS835F—October 2013
1.2 Applications
• Small Cell
1.3 KeyStone Architecture
TI’s KeyStone Multicore Architecture provides a high performance structure for integrating RISC and DSP cores
with application-specific coprocessors and I/O. KeyStone is the first of its kind in that it provides adequate internal
bandwidth for nonblocking access to all processing cores, peripherals, coprocessors, and I/O. This is achieved with
four main hardware elements: Multicore Navigator, TeraNet, Multicore Shared Memory Controller, and
HyperLink.
Multicore Navigator is an innovative packet-based manager that controls 16k queues. When tasks are allocated to
the queues, Multicore Navigator provides hardware-accelerated dispatch that directs tasks to the appropriate
available hardware. The packet-based system on a chip (SoC) uses the 2-Tbps capacity of the TeraNet switched
central resource to move packets. The Multicore Shared Memory Controller enables processing cores to access
shared memory directly without drawing from the TeraNet’s capacity, so packet movement cannot be blocked by
memory access.
HyperLink provides a 50-GBaud chip-level interconnect that allows SoCs to work in tandem. Its low-protocol
overhead and high throughput make HyperLink an ideal interface for chip-to-chip interconnections. Working with
Multicore Navigator, HyperLink dispatches tasks to tandem devices transparently and executes tasks as if they are
running on local resources.
1.4 Device Description
The TCI6636K2H Communications Infrastructure KeyStone SoC is a member of the C66x family based on TI's new
KeyStone II Multicore SoC Architecture designed specifically for high performance wireless infrastructure
applications. The TCI6636K2H provides a very high performance macro basestation platform for developing all
wireless standards including WCDMA/HSPA/HSPA+, TD-SCDMA, GSM, TDD-LTE, FDD-LTE, and WiMAX.
TI's KeyStone II Architecture provides a programmable platform integrating various subsystems (ARM CorePac,
C66x CorePacs, IP network, radio layers 1, 2, and 3, and transport processing) and uses a queue-based
communication system that allows the SoC resources to operate efficiently and seamlessly. This unique SoC
architecture also includes a TeraNet switch that enables the wide mix of system elements, from programmable cores
to dedicated coprocessors and high-speed IO, to each operate at maximum efficiency with no blocking or stalling.
The addition of the ARM CorePac in the TCI6636K2H enables the ability for layer 2 and layer 3 processing on-chip.
Operations such as Traffic Control, Local O&M, NBAP/FP termination, and SCTP processing can all be performed
with the Cortex-A15 processor.
TI's new C66x core launches a new era of DSP technology by combining fixed-point and floating-point
computational capability in the processor without sacrificing speed, size, or power consumption. The raw
computational performance is an industry-leading 38.4 GMACS/core and 19.2 Gflops/core (@ 1.2 GHz operating
frequency). The C66x is also 100% backward compatible with software for C64x+ devices. The C66x CorePac
incorporates 90 new instructions targeted for floating point (FPi) and vector math oriented (VPi) processing. These
enhancements yield tremendous performance improvements in multi-antenna 4.8G signal processing for
algorithms like MIMO and beamforming.
2 TCI6636K2H Features and Description
Copyright 2013 Texas Instruments Incorporated
Submit Documentation Feedback