TCI6636K2H Datasheet, PDF (240/362 Pages) Texas Instruments – Multicore DSP+ARM KeyStone II System-on-Chip (SoC)

TCI6636K2H
Multicore DSP+ARM KeyStone II System-on-Chip (SoC)
SPRS835F—October 2013
8.2.3.4 Kicker Mechanism (KICK0 and KICK1) Register
The Bootcfg module contains a kicker mechanism to prevent spurious writes from changing any of the Bootcfg
MMR (memory mapped registers) values. When the kicker is locked (which it is initially after power on reset), none
of the Bootcfg MMRs are writable (they are only readable). This mechanism requires an MMR write to each of the
KICK0 and KICK1 registers with exact data values before the kicker lock mechanism is unlocked. See
Table 8-30 ‘‘Device State Control Registers’’ on page 234 for the address location. Once released, all the Bootcfg
MMRs having write permissions are writable (the read only MMRs are still read only). The KICK0 data is
0x83e70b13. The KICK1 data is 0x95a4f1e0. Writing any other data value to either of these kick MMRs locks the
kicker mechanism and blocks writes to Bootcfg MMRs. To ensure protection to all Bootcfg MMRs, software must
always re-lock the kicker mechanism after completing the MMR writes.
8.2.3.5 LRESETNMI PIN Status (LRSTNMIPINSTAT) Register
The LRSTNMIPINSTAT Register latches the status of LRESET and NMI based on the setting of CORESEL[2:0]. The
LRESETNMI PIN Status Register is shown in the figure and table below.
Figure 8-16 LRESETNMI PIN Status Register (LRSTNMIPINSTAT)
31
16
15
14
13
12 11 10 9 8 7 6 5 4
3
21
0
Reserved
NMI7 NMI6 NMI5 NMI4 NMI3 NMI2 NMI1 NMI0 LR7 LR6 LR5 LR4 LR3 LR2 LR1 LR0
R-0
R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0
Legend: R = Read only; -n = value after reset
Table 8-34 LRESETNMI PIN Status Register Field Descriptions
Bit Field
31-16 Reserved
15 NMI7
14 NMI6
13 NMI5
12 NM4
11 NMI3
10 NMI2
9
NMI1
8
NMI0
7
LR7
6
LR6
5
LR5
4
LR4
3
LR3
2
LR2
1
LR1
0
LR0
End of Table 8-34
Description
Reserved
C66x CorePac7 in NMI
C66x CorePac6 in NMI
C66x CorePac5 in NMI
C66x CorePac4 in NMI
C66x CorePac3 in NMI
C66x CorePac2 in NMI
C66x CorePac1 in NMI
C66x CorePac0 in NMI
C66x CorePac7 in Local Reset
C66x CorePac6 in Local Reset
C66x CorePac5 in Local Reset
C66x CorePac4 in Local Reset
C66x CorePac3 in Local Reset
C66x CorePac2 in Local Reset
C66x CorePac1 in Local Reset
C66x CorePac0 in Local Reset
240 Device Boot and Configuration
Copyright 2013 Texas Instruments Incorporated
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