TCI6636K2H Datasheet, PDF (319/362 Pages) Texas Instruments – Multicore DSP+ARM KeyStone II System-on-Chip (SoC)

Table 10-38 I²C Registers (Part 2 of 2)
Hex Address Offsets
Acronym
0x0034
ICPID1
0x0038
ICPID2
0x003C -0x007F
-
End of Table 10-38
TCI6636K2H
Multicore DSP+ARM KeyStone II System-on-Chip (SoC)
SPRS835F—October 2013
Register Name
I²C Peripheral Identification Register 1 [value: 0x0000 0105]
I²C Peripheral Identification Register 2 [value: 0x0000 0005]
Reserved
10.10.3 I²C Electrical Data/Timing
10.10.3.1 Inter-Integrated Circuits (I²C) Timing
Table 10-39 I²C Timing Requirements ⁽¹⁾
(see Figure 10-35)
Standard Mode
Fast Mode
No.
Min
Max
Min Max Units
1
t_c(SCL)
Cycle time, SCL
10
2
t_{su(SCLH-SDAL)}
Setup time, SCL high before SDA low (for a repeated START
condition)
4.7
2.5
μs
0.6
μs
3
t_h(SDAL-SCLL)
Hold time, SCL low after SDA low (for a START and a repeated
START condition)
4
0.6
μs
4
t_w(SCLL)
Pulse duration, SCL low
4.7
1.3
μs
5
t_w(SCLH)
Pulse duration, SCL high
6 t_{su(SDAV-SCLH)} Setup time, SDA valid before SCL high
7
t_h(SCLL-SDAV)
Hold time, SDA valid after SCL low (for I²C bus devices)
4
250
0 ⁽³⁾
3.45
0.6
100 ⁽²⁾
0 ⁽³⁾
μs
ns
0.9 ⁽⁴⁾ μs
8
t_w(SDAH)
9
t_r(SDA)
10 t_r(SCL)
11 t_f(SDA)
12 t_f(SCL)
Pulse duration, SDA high between STOP and START conditions
Rise time, SDA
Rise time, SCL
Fall time, SDA
Fall time, SCL
4.7
1.3
μs
1000
1000
300
300
20 + 0.1C_b ⁽⁵⁾
20 + 0.1C_b ⁽⁵⁾
20 + 0.1C_b ⁽⁵⁾
20 + 0.1C_b ⁽⁵⁾
300 ns
300 ns
300 ns
300 ns
13 t_{su(SCLH-SDAH)} Setup time, SCL high before SDA high (for STOP condition)
4
0.6
μs
14 t_w(SP)
C_b ⁽⁵⁾
End of Table 10-39
Pulse duration, spike (must be suppressed)
Capacitive load for each bus line
0
50 ns
400
400 pF
1 The I²C pins SDA and SCL do not feature fail-safe I/O buffers. These pins could potentially draw current when the device is powered down.
2 A Fast-mode I²C-bus device can be used in a Standard-mode I²C-bus system, but the requirement tsu(SDA-SCLH) ≥ 250 ns must then be met. This will automatically be the
case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the
SDA line t_r max + t_su(SDA-SCLH) = 1000 + 250 = 1250 ns (according to the Standard-mode I²C-Bus Specification) before the SCL line is released.
3 A device must internally provide a hold time of at least 300 ns for the SDA signal (referred to the V_IHmin of the SCL signal) to bridge the undefined region of the falling edge
of SCL.
4 The maximum t_h(SDA-SCLL) has to be met only if the device does not stretch the low period [t_w(SCLL)] of the SCL signal.
5 C_b = total capacitance of one bus line in pF. If mixed with HS-mode devices, faster fall-times are allowed.
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TCI6636K2H Peripheral Information and Electrical Specifications 319